- General Chair:
- Laxmi N. Bhuyan,
- Program Chairs:
- Michel Dubois,
- Will Eatherton
On behalf of the program committee we are both pleased to welcome you to the second edition of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS) held in San Jose.Our goal from the beginning was to build on last year's success and establish ANCS as the premier research conference dedicated to the design of the hardware and software components used to create modern communication networks. This year's program is diverse and includes papers on switches, routers and interconnection networks, packet processing, network processor design, scheduling and security.The selection of the technical papers offered in this conference results from a long and rigorous process. The quality of any conference is derived from the quality of the submitted papers and the quality of the paper selection process. This conference is indebted to all authors who submitted their best work and to the program committee made of experts in the field. We were fortunate to recruit an outstanding program committee of 22 members who graciously contributed their time and expertise towards the success of the conference.We received 97 submissions from all over the world. Of these, 23 manuscripts were withdrawn by the authors before the review process started or were deemed out of scope for the conference. Each of the 74 remaining papers was then reviewed by at least one committee member and by two additional reviewers. Every paper received at least three reviews mostly from program committee members. The committee meeting took place on Friday September 22 in one day. The review process was "double-blind". Authors' identities were kept anonymous throughout the meeting, except that program committee members had to leave the meeting at times to avoid conflicts of interest. Papers co-authored by program committee members were treated like all other papers during the entire process.At the end the program committee accepted 19 papers which will be presented in single tracks over the two days of the conference. We hope that all of you will find the program enjoyable, stimulating and useful to your career, for this would be the best reward for all the work that went into its preparation.
Proceeding Downloads
A proposed architecture for the GENI backbone platform
The GENI Project (Global Environment for Network Innovation) is a major NSF-sponsored initiative that seeks to create a national research facility to enable experimental deployment of innovative new network architectures on a sufficient scale to enable ...
Towards an efficient switch architecture for high-radix switches
The interconnection network plays a key role in the overall performance achieved by high performance computing systems, also contributing an increasing fraction of its cost and power consumption. Current trends in interconnection network technology ...
A practical fast parallel routing architecture for Clos networks
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos networks, sequential routing algorithms are too slow, and all known parallel ...
Design of a web switch in a reconfigurable platform
The increase of the web traffic has created the need for web switches that are able to balance the traffic to the server farms based on their contents (e.g. layer 7 switching). In this paper we present a web switch implemented in a multi-processor ...
Packet classification using coarse-grained tuple spaces
While the problem of high performance packet classification has received a great deal of attention in recent years, the research community has yet to develop algorithmic methods that can overcome the drawbacks of TCAM-based solutions. This paper ...
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been proposed, which delivers very high lookup and update throughput. These ...
Fast packet classification using bloom filters
Ternary Content Addressable Memory (TCAM), although widely used for general packet classification, is an expensive and high power-consuming device. Algorithmic solutions which rely on commodity memory chips are relatively inexpensive and power-efficient ...
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and content-aware switch etc. The increasing line speed and expanding pattern ...
Advanced algorithms for fast and scalable deep packet inspection
Modern deep packet inspection systems use regular expressions to define various patterns of interest in network data streams. Deterministic Finite Automata (DFA) are commonly used to parse regular expressions. DFAs are fast, but can require ...
Fast and memory-efficient regular expression matching for deep packet inspection
Packet content scanning at high speed has become extremely important due to its applications in network security, network monitoring, HTTP load balancing, etc. In content scanning, the packet payload is compared against a set of patterns specified as ...
An effective network processor design framework: using multi-objective evolutionary algorithms and object oriented techniques to optimise the intel IXP1200 network processor
In this paper we present a framework for design space exploration of a network processor, that incorporates parameterisation, power and cost analysis. This method utilises multi-objective evolutionary algorithms and object oriented analysis and design. ...
A methodology for evaluating runtime support in network processors
Modern network processor systems require the ability to adapt their processing capabilities at runtime to changes in network traffic. Traditionally, network processor applications have been optimized for a single static workload scenario, but recently ...
High-throughput sketch update on a low-power stream processor
Sketch algorithms are widely used for many networking applications, such as identifying frequent items, top-k flows, and traffic anomalies. This paper explores the implementation of the Count-Min sketch update using Indexed SRF accesses on a SIMD stream ...
Symerton--using virtualization to accelerate packet processing
The complexity of packet-processing applications continues to grow, with encryption, compression, and XML processing becoming common on packet-processing devices at the edge of enterprise and service provider networks. While performance remains a key ...
Sequence-preserving adaptive load balancers
Load balancing in packet-switched networks is a task of ever-growing importance. Network traffic properties, such as the Zipf-like flow length distribution and bursty transmission patterns, and requirements on packet ordering or stable flow mapping, ...
Localized asynchronous packet scheduling for buffered crossbar switches
Buffered crossbar switches are a special type of crossbar switches. In such a switch, besides normal input queues and output queues, a small buffer is associated with each crosspoint. Due to the introduction of crosspoint buffers, output and input ...
Scalable network-based buffer overflow attack detection
Buffer overflow attack is the main attack method that most if not all existing malicious worms use to propagate themselves from machine to machine. Although a great deal of research has been invested in defense mechanisms against buffer overflow attack, ...
WormTerminator: an effective containment of unknown and polymorphic fast spreading worms
The fast spreading worm is becoming one of the most serious threats to today's networked information systems. A fast spreading worm could infect hundreds of thousands of hosts within a few minutes. In order to stop a fast spreading worm, we need the ...
Packet pre-filtering for network intrusion detection
As Intrusion Detection Systems (IDS)utilize more complex syntax to efficiently describe complex attacks, their processing requirements increase rapidly. Hardware and, even more, software platforms face difficulties in keeping up with the computationally ...
- Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems