research-article

Energy and Area Efficient Near Field Inductive Coupling: A Case Study on 3D NoC

Authors:

Srinivasan Gopal,

Partha Pratim PandeAuthors Info & Claims

NOCS '17: Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip

Article No.: 5, Pages 1 - 8

https://doi.org/10.1145/3130218.3130224

Published: 19 October 2017 Publication History

Abstract

Near Field Inductive Coupling (NFIC) enables design of energy efficient and robust three-dimensional (3D) manycore systems. The associated design challenges and the trade-offs of the NFIC-based vertical links depend on achievable data-rates, energy and area overheads. In this work, we propose a holistic design flow that explores optimum energy and area efficient NFIC-link design as a communication backbone in a 3D manycore chip. Moreover, the design framework employs statistical link analysis to select optimum NFIC link configuration. The proposed NFIC-link design is significantly more efficient in terms of energy efficiency and area overhead compared to state-of-the-art counterpart. Energy efficiency and resiliency of NFIC-links are exploited in the context of a 3D NoC design. We demonstrate that overall reliability of the NFIC-enabled 3D NoC is significantly better compared to a conventional stand-alone TSV-based architecture.

References

[1]

Anna W. Topol et al., "Three-dimensional integrated circuits," in IBM Journal of Research and Dev., vol. 50, no. 4.5, pp. 491--506, July 2006.

Digital Library

[2]

W. R. Davis et al., "Demystifying 3D ICs: the pros and cons of going vertical," in IEEE Design and Test of Computers, vol. 22, 6, pp. 498--510, Nov.-Dec. 2005.

Digital Library

[3]

G. H. Loh, "3D-Stacked Memory Architectures for Multi-core Processors," in Symp. on Computer Architecture, 2008, pp. 453--464.

Digital Library

[4]

A. C. Hsieh, T.T. Hwang "TSV Redundancy: Architecture and Design Issues in 3-D IC," in IEEE TVLSI, vol.20, no. 4, pp.711--722, April 2012.

Digital Library

[5]

S. Das et. al. "Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach", in ICCAD, 2015, pp. 705--712.

Digital Library

[6]

H. Matsutani, et al. "Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips", in Proc. of DATE, 2014.

Digital Library

[7]

D. Ditzel, T. Kuroda, and S. Lee, "Low-cost 3D chip stacking with ThruChip wireless connections," in Proc. of IEEE Hot Chips, Aug. 2014.

[8]

M. Hossain and A. Chan Carusone, "5--10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS," in IEEE JSSC, vol.45 no. 3, pp. 524, March 2010.

[9]

T. Kagami, et. al. "Efficient 3-D bus architectures for inductive-coupling thruchip interfaces," in IEEE TVLSI, vol. 24, no. 2, pp. 493--506, Feb 2016.

[10]

D. Dutoit et al., "A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC," in Symposium on VLSIT, Jun. 2013, pp. C22--C23.

[11]

G. V. d. Plas et. al., "Design issues and considerations for low-cost 3-D TSV IC technology," IEEE JSSC, vol. 46, no.1, pp. 293, Jan. 2011.

[12]

Y. Liu, et. al. "A compact low-power 3d i/o in 45 nm CMOS", in ISSCC 2012.

[13]

Q. Gu et al., "Two 10 Gb/s/pin low-power interconnect methods for 3-D ICs," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 448--449.

[14]

Y. Take et al., "3D NoC with inductive-coupling links for building-block SiPs," IEEE Trans. on Computers, vol. 63, (3), Mar. 2014.

Digital Library

[15]

B. S. Feero, P.P. Pande "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation", in IEEE TC, Vol 53, Aug. 2008.

Digital Library

[16]

J. Baylon et. al. "Current Reuse Triple-Band Signal Source for Multi-Band Wireless Network-on-Chip" in IEEE MTT-S IMS, Honolulu, HI, 2017, pp. 1--4.

[17]

A. M. Rahmani, et al. "High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET Based Adaptive Monitoring Platform", IEEE Trans. on Computers, vol 63, Mar 2014.

Digital Library

[18]

M. del M. Hershenson, et. al. "Optimization of inductor circuits via geometric programming." in DAC, pp. 994--998. ACM, 1999.

Digital Library

[19]

R. Sredojevic, et.al. "Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high speed link example," in ICCAD, 2008, pp. 314--321.

Digital Library

[20]

A. Palaniappan and S. Palermo, "A design methodology for power efficiency optimization of high-speed equalized-electrical I/O architectures," IEEE TVLSI., vol. 21, (8), pp. 1421--1431, Aug. 2013.

Digital Library

[21]

O. Lysne, T. Skeie, S. A. Reinemo, I. Theiss, "Layered Routing in Irregular Networks", IEEE TPDS, vol. 17, pp. 51-- 65, 2006.

Digital Library

[22]

S. C. Woo et al. "The SPLASH-2 programs: characterization and methodological considerations," in ISCA, 1995, pp. 24--36.

Digital Library

[23]

C. Bienia, "Benchmarking modern multiprocessors," Ph.D. Dissertation, Princeton Univ., Princeton NJ, Jan. 2011.

Digital Library

[24]

P. M. Yaghini et. al. "Capacitive and Inductive TSV-to-TSV Resilient approaches for 3D ICs," in IEEE Trans. on Computers, vol. 65, 3, March 2016.

Digital Library

[25]

S. Wang, M. B. Tahoori and K. Chakrabarty. "Thermal-aware TSV repair for electromigration in 3D ICs," in Proc. of DATE, 2016, pp. 1291--1296.

Digital Library

[26]

T. Frank et al., "Electromigration behavior of 3D-IC TSV interconnects," in ECTC, 2012, pp. 326--330.

[27]

S. K. Samal, D. Nayak, M. Ichihashi, S. Banna and S. K. Lim, "Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology," in S3S, 2016, pp. 1--2.

Cited By

Kayashima HAmano H(2021)Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW53999.2021.00055(292-296)Online publication date: Nov-2021
https://doi.org/10.1109/CANDARW53999.2021.00055
Gopal SDas SPande PHeo D(2020)A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoCIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.301309267:11(3919-3932)Online publication date: Nov-2020
https://doi.org/10.1109/TCSI.2020.3013092
Ahmed MVashist APudukotai Dinakarrao SGanguly A(2020)Architecting a Secure Wireless Interconnect for Multichip Communication: An ML Approach2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST51057.2020.9358256(1-6)Online publication date: 15-Dec-2020
https://doi.org/10.1109/AsianHOST51057.2020.9358256
Show More Cited By

Index Terms

Energy and Area Efficient Near Field Inductive Coupling: A Case Study on 3D NoC
1. Hardware
  1. Integrated circuits
    1. 3D integrated circuits
2. Networks
  1. Network types
    1. Network on chip

Recommendations

Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures
GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Three dimensional (3D) Network-on-Chip (NoC) architectures enable design of low power and high performance communication fabrics for multicore chips. In spite of achievable performance benefits, 3D NoCs are still bottlenecked by the planar ...
Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture
Abstract
The emergence of three-dimensional (3D) network-on-chip (NoC) has revolutionized the design of high-performance and energy efficient manycore chips. However, in general, 3D NoC architectures still suffer from high power density and the ...
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction
GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI

Interconnect area and energy dissipation are critical factors in any system designed today. In this work, we present techniques to help reduce area/cost and energy dissipation of address buses with significant temporal redundancy. We describe two ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

NOCS '17: Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip

October 2017

170 pages

ISBN:9781450349840

DOI:10.1145/3130218

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 October 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

NOCS '17

Sponsor:

NOCS '17: International Symposium on Networks-on-Chip

October 19 - 20, 2017

Seoul, Republic of Korea

Acceptance Rates

NOCS '17 Paper Acceptance Rate 14 of 44 submissions, 32%;

Overall Acceptance Rate 14 of 44 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
169
Total Downloads

Downloads (Last 12 months)20
Downloads (Last 6 weeks)0

Reflects downloads up to 27 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Kayashima HAmano H(2021)Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW53999.2021.00055(292-296)Online publication date: Nov-2021
https://doi.org/10.1109/CANDARW53999.2021.00055
Gopal SDas SPande PHeo D(2020)A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoCIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.301309267:11(3919-3932)Online publication date: Nov-2020
https://doi.org/10.1109/TCSI.2020.3013092
Ahmed MVashist APudukotai Dinakarrao SGanguly A(2020)Architecting a Secure Wireless Interconnect for Multichip Communication: An ML Approach2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)10.1109/AsianHOST51057.2020.9358256(1-6)Online publication date: 15-Dec-2020
https://doi.org/10.1109/AsianHOST51057.2020.9358256
Koibuchi MLeong LTotoki TNiwa NMatsutani HAmano HCasanova H(2019)Sparse 3-D NoCs with Inductive CouplingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317913(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317913
Kayashima HKojima TOkuhara HShidei TAmano H(2019)Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process2019 Seventh International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW.2019.00054(269-274)Online publication date: Nov-2019
https://doi.org/10.1109/CANDARW.2019.00054
Gopal SHeo DKarnik T(2019)Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface2019 International 3D Systems Integration Conference (3DIC)10.1109/3DIC48104.2019.9058859(1-6)Online publication date: Oct-2019
https://doi.org/10.1109/3DIC48104.2019.9058859
Gopal SDas SAgarwal PAli SHeo DPande P(2018)High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoCIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.286570426:12(2921-2934)Online publication date: Dec-2018
https://doi.org/10.1109/TVLSI.2018.2865704
Baylon JYu XGopal SMolavi RMirabbasi SPande PHeo D(2018)A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-ChipIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285689026:11(2406-2418)Online publication date: Nov-2018
https://doi.org/10.1109/TVLSI.2018.2856890
Gopal SAgarwal PAli SBaylon JHeo D(2018)An Echo-Canceller-Iess NFIC- TSV Hybrid 3D Interconnect for Simultaneous Bidirectional Vertical Communication2018 IEEE/MTT-S International Microwave Symposium - IMS10.1109/MWSYM.2018.8439430(663-666)Online publication date: Jun-2018
https://doi.org/10.1109/MWSYM.2018.8439430

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents