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Demystifying 3D ICs: The Pros and Cons of Going Vertical

Published: 01 November 2005 Publication History

Abstract

As 3D technologies become technologically viable, there is increasinginterest in determining the achievable payoff. This article first presents an overview of 3D technologies and introduces the motivation for moving from 2D to 3D. It then presents a case study of a fast-Fourier-transform design to illustrate the advantages of going to the third dimension.

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V. Suntharalingam et al., "Megapixel CMOS Image Sensor Fabricated in Three-Dimensional Integrated Circuit Technology," Int'l Solid-State Circuits Conf. Digest of Technical Papers (ISSCC 05), IEEE Press, 2005, pp. 356-357.
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Cited By

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  • (2024)An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.343049832:10(1769-1781)Online publication date: 1-Oct-2024
  • (2024)An Evaluation Framework for Dynamic Thermal Management Strategies in 3D MultiProcessor System-on-Chip Co-DesignIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2024.345941435:11(2161-2176)Online publication date: 1-Nov-2024
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Information

Published In

cover image IEEE Design & Test
IEEE Design & Test  Volume 22, Issue 6
November 2005
118 pages

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 November 2005

Author Tags

  1. C.0.e System architectures
  2. I/O and Data Communications
  3. Interconnection architectures
  4. Parallel I/O
  5. Placement and routing
  6. Receivers
  7. Routing and layout
  8. Transmitters
  9. integration and modeling

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Cited By

View all
  • (2024)A Cost-Driven Chip Partitioning Method for Heterogeneous 3D IntegrationACM Transactions on Design Automation of Electronic Systems10.1145/367255829:4(1-27)Online publication date: 14-Jun-2024
  • (2024)An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.343049832:10(1769-1781)Online publication date: 1-Oct-2024
  • (2024)An Evaluation Framework for Dynamic Thermal Management Strategies in 3D MultiProcessor System-on-Chip Co-DesignIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2024.345941435:11(2161-2176)Online publication date: 1-Nov-2024
  • (2024)Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337125543:8(2249-2262)Online publication date: 1-Aug-2024
  • (2023)Routing in 3D NoCs Using Genetic Algorithm and Particle Swarm OptimizationComputational Science and Its Applications – ICCSA 2023 Workshops10.1007/978-3-031-37105-9_40(601-613)Online publication date: 3-Jul-2023
  • (2021)Power Management of Monolithic 3D Manycore Chips with Inter-tier Process VariationsACM Journal on Emerging Technologies in Computing Systems10.1145/343076517:2(1-19)Online publication date: 6-Jan-2021
  • (2021)HeM3DACM Transactions on Design Automation of Electronic Systems10.1145/342423926:2(1-21)Online publication date: 17-Feb-2021
  • (2021)Vertical traversal approach towards TSVs optimisation over multilayer network on chip (NoC)Microelectronics Journal10.1016/j.mejo.2021.105231116:COnline publication date: 1-Oct-2021
  • (2021)Floor Planning of 3D IC Design Using Hybrid Multi-verse OptimizerWireless Personal Communications: An International Journal10.1007/s11277-021-08166-z118:4(3007-3023)Online publication date: 1-Jun-2021
  • (2021)An analysis of the eddy effect in through-silicon vias based on Cu and CNT bundles: the impact on crosstalk and powerJournal of Computational Electronics10.1007/s10825-021-01776-720:6(2456-2470)Online publication date: 1-Dec-2021
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