research-article

Low-latency wireless 3D NoCs via randomized shortcut chips

Authors:

Hiroki Matsutani,

Michihiro Koibuchi,

Takahiro Kagami,

Tadahiro Kuroda,

Radu Marculescu,

Hideharu AmanoAuthors Info & Claims

DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

Article No.: 273, Pages 1 - 6

Published: 24 March 2014 Publication History

Abstract

In this paper, we demonstrate that we can reduce the communication latency significantly by inserting a fraction of randomness into a wireless 3D NoC (where CMOS wireless links are used for vertical inter-chip communication) when considering the physical constraints of the 3D design space. Towards this end, we consider two cases, namely 1) replacing existing horizontal 2D links in a wireless 3D NoC with randomized shortcut NoC links and 2) enabling full connectivity by adding a randomized NoC layer to a wireless 3D platform with partial or no horizontal connectivity. Consequently, the packet routing is optimized by exploiting both the existing and the newly added random NoC. At the same time, by adding randomly wired shortcut NoCs to a wireless 3D platform, a good balance can be established between the modularity of the design and the minimum randomness needed to achieve low latency, and experimental results show that by adding a random NoC chip to wireless 3D CMPs without built-in horizontal connectivity, the communication latency can be reduced by as much as 26.2% when compared to adding a 2D mesh NoC. Also, the application execution time and average flit transfer energy can be improved accordingly.

References

[1]

W. R. Davis et al., "Demystifying 3D ICs: The Pros and Cons of Going Vertical," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 498--510, Nov. 2005.

Digital Library

[2]

N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, "A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping," in Proceedings of the International Solid-State Circuits Conference (ISSCC'07), Feb. 2007, pp. 358--359.

[3]

S. Saito et al., "MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link," in Proceedings of the Field-Programmable Logic and Applications (FPL'09), Sep. 2009, pp. 6--11.

[4]

M. D. Schroeder et al., "Autonet: A High-speed, Self-configuring Local Area Network Using Point-to-point Links," IEEE Journal on Selected Areas in Communications, vol. 9, pp. 1318--1335, Oct. 1991.

Digital Library

[5]

H. Matsutani, P. Bogdan, R. Marculescu, Y. Take, D. Sasaki, H. Zhang, M. Koibuchi, T. Kuroda, and H. Amano, "A Case for Wireless 3D NoCs for CMPs," in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'13), Jan. 2013, pp. 22--28.

[6]

M. Koibuchi, H. Matsutani, H. Amano, D. F. Hsu, and H. Casanova, "A Case for Random Shortcut Topologies for HPC Interconnects," in Proceedings of the International Symposium on Computer Architecture (ISCA'12), 2012, pp. 177--188.

Digital Library

[7]

A. Singla, C.-Y. Hong, L. Popa, and P. B. Godfrey, "Jellyfish: Networking Data Centers Randomly," in Proceedings of the USENIX conference on Networked Systems Design and Implementation (NSDI'12), Oct. 2012.

Digital Library

[8]

U. Y. Ogras and R. Marculescu, "It's a Small World After All: NoC Performance Optimization via Long-Range Link Insertion," IEEE Transactions on Very Large Scale Integration Systems, vol. 14, pp. 693--706, 2006.

Digital Library

[9]

A. Ganguly, K. Chang, S. Deb, P. P. Pande, B. Belzer, and C. Teuscher, "Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-core Systems," IEEE Transactions on Computers, vol. 60, no. 10, pp. 1485--1502, Oct. 2011.

Digital Library

[10]

S. J. Hollis, C. Jackson, P. Bogdan, and R. Marculescu, "Exploiting Emergence in On-chip Interconnects," IEEE Transactions on Computers, Nov. 2012, (PrePrint).

Digital Library

[11]

D. J. Watts and S. H. Strogatz, "Collective Dynamics of 'Small-World' Networks," Nature, vol. 393, no. 6684, pp. 440--442, 1998.

[12]

H. Matsutani, Y. Take, D. Sasaki, M. Kimura, Y. Ono, Y. Nishiyama, M. Koibuchi, T. Kuroda, and H. Amano, "A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs," in Proceedings of the International Symposium on Networks-on-Chip (NOCS'11), May 2011, pp. 49--56.

Digital Library

[13]

T. D. Richardson, C. Nicopoulos, D. Park, V. Narayanan, Y. Xie, C. Das, and V. Degalahal, "A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks," in Proceedings of International Conference on VLSI Design (VLSID'06), Jan. 2006, pp. 657--664.

Digital Library

[14]

M. O. Agyeman, A. Ahmadinia, and A. Shahrabi, "Low Power Heterogeneous 3D Networks-on-Chip Architectures," in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS'11), Jul. 2011, pp. 533--538.

[15]

N. Binkert et al., "The gem5 Simulator," ACM SIGARCH Computer Architecture News, vol. 39, no. 2, pp. 1--7, May 2011.

Digital Library

Cited By

Gade SAhmed MDeb SGanguly A(2019)Energy Efficient Chip-to-Chip Wireless Interconnection for Heterogeneous ArchitecturesACM Transactions on Design Automation of Electronic Systems10.1145/334010924:5(1-27)Online publication date: 26-Jul-2019
https://dl.acm.org/doi/10.1145/3340109
Koibuchi MLeong LTotoki TNiwa NMatsutani HAmano HCasanova H(2019)Sparse 3-D NoCs with Inductive CouplingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317913(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317913
Nakao MMurai HSato M(2019)A Method for Order/Degree Problem Based on Graph Symmetry and Simulated Annealing with MPI/OpenMP ParallelizationProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3293320.3293325(128-137)Online publication date: 14-Jan-2019
https://dl.acm.org/doi/10.1145/3293320.3293325
Show More Cited By

Index Terms

Low-latency wireless 3D NoCs via randomized shortcut chips
1. Hardware

Recommendations

XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs
NOCS '17: Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip

In this paper, we propose a method to design low latency and low energy networks for 3D Network-on-Chip (3D-NoC). Recent many-core processors require low-latency interconnection networks since the increasing number of cores limits the network ...
Optimized Core-Links for Low-Latency NoCs
PDP '15: Proceedings of the 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

In recent many-core architectures, the number of cores has been steadily increasing and thus the network latency between cores becomes an important issue for parallel application programs. Because packet-switched network structures are widely used for ...
Time-Randomized Wormhole NoCs for Critical Applications
Special Issue on Emerging Networks-on-Chip and Regular Papers

Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Other conferences

DATE '14: Proceedings of the conference on Design, Automation & Test in Europe

March 2014

1959 pages

ISBN:9783981537024

General Chairs:
Gerhard Fettweis
TU Dresden, DE
,
Wolfgang Nebel
OFFIS, DE

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

In-Cooperation

SIGDA: ACM Special Interest Group on Design Automation

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 24 March 2014

Check for updates

Qualifiers

Research-article

Conference

DATE '14

Sponsor:

EDAA
EDAC
The Russian Academy of Sciences

DATE '14: Design, Automation and Test in Europe

March 24 - 28, 2014

Dresden, Germany

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
80
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 24 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Gade SAhmed MDeb SGanguly A(2019)Energy Efficient Chip-to-Chip Wireless Interconnection for Heterogeneous ArchitecturesACM Transactions on Design Automation of Electronic Systems10.1145/334010924:5(1-27)Online publication date: 26-Jul-2019
https://dl.acm.org/doi/10.1145/3340109
Koibuchi MLeong LTotoki TNiwa NMatsutani HAmano HCasanova H(2019)Sparse 3-D NoCs with Inductive CouplingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317913(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317913
Nakao MMurai HSato M(2019)A Method for Order/Degree Problem Based on Graph Symmetry and Simulated Annealing with MPI/OpenMP ParallelizationProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3293320.3293325(128-137)Online publication date: 14-Jan-2019
https://dl.acm.org/doi/10.1145/3293320.3293325
Lee DDas SKim DDoppa JPande P(2018)Design Space Exploration of 3D Network-on-ChipACM Journal on Emerging Technologies in Computing Systems10.1145/319756714:3(1-26)Online publication date: 23-Oct-2018
https://dl.acm.org/doi/10.1145/3197567
Mohseni ZReshadi M(2018)A deadlock-free routing algorithm for irregular 3D network-on-chips with wireless linksThe Journal of Supercomputing10.1007/s11227-017-2173-974:2(953-969)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1007/s11227-017-2173-9
Nakahara HDoan NYasudo RAmano H(2017)XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCsProceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip10.1145/3130218.3130232(1-8)Online publication date: 19-Oct-2017
https://dl.acm.org/doi/10.1145/3130218.3130232
Gopal SDas SHeo DPande P(2017)Energy and Area Efficient Near Field Inductive CouplingProceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip10.1145/3130218.3130224(1-8)Online publication date: 19-Oct-2017
https://dl.acm.org/doi/10.1145/3130218.3130224
Chittamuru SDesai SPasricha S(2017)SWIFTNoCACM Journal on Emerging Technologies in Computing Systems10.1145/306051713:4(1-27)Online publication date: 29-Jun-2017
https://dl.acm.org/doi/10.1145/3060517
Kiani VReshadi M(2017)Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless linksThe Journal of Supercomputing10.1007/s11227-016-1908-373:5(2187-2213)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1007/s11227-016-1908-3
Das SDoppa JKim DPande PChakrabarty KMarculescu DLiu F(2015)Optimizing 3D NoC Design for Energy EfficiencyProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840917(705-712)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840917
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents