DLIC: Decoded loop instructions caching for energy-aware embedded processors
Authors: 
Ji Gu, Hui Guo, Tohru IshiharaAuthors Info & Claims
Article No.: 6, Pages 1 - 26
Abstract
With the explosive proliferation of embedded systems, especially through countless portable devices and wireless equipment used, embedded systems have become indispensable to the modern society and people's life. Those devices are often battery driven. Therefore, low energy consumption in embedded processors is important and becomes critical in step with the system complexity. The on-chip instruction cache (I-cache) is usually the most energy-consuming component on the processor chip due to its large size and frequent access operations. To reduce such energy consumption, the existing loop cache approaches use a tiny decoded cache to filter the I-cache access and instruction decode activity for repeated loop iterations. However, such designs are effective for small and simple loops, and only suitable for DSP kernel-like applications. They are not effectual for many embedded applications where complex loops are common. In this article, we propose a decoded loop instruction cache (DLIC) that is small, hence energy efficient, yet can capture most loops, including large nested ones with branch executions, so that a significant amount of I-cache accesses and instruction decoding can be eradicated. The experiments on a set of embedded benchmarks show that our proposed DLIC scheme can reduce energy consumption by up to 87% as compared to normal cache-only design. On average, 66% energy can be saved on instruction fetching and decoding, while at a performance overhead of only 1.4%.
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Index Terms
- DLIC: Decoded loop instructions caching for energy-aware embedded processors
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Publication History
Published: 05 September 2013
Accepted: 01 May 2012
Revised: 01 July 2011
Received: 01 November 2010
Published in TECS Volume 13, Issue 1
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