Article

Analysis and design of low-energy flip-flops

Authors:

Dejan Markovic,

Borivoje Nikolic,

Robert BrodersenAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 52 - 55

https://doi.org/10.1145/383082.383093

Published: 06 August 2001 Publication History

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References

[1]

H. Partovi, "Clocked storage elements," in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W.J. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE Press, 2000, pp. 207-234.

Google Scholar

[2]

G. Gerosa et al., "A 2.2W, 80 MHz superscalar RISC microprocessor," IEEE J. Solid-State Circuits, vol. 29, pp. 1440-1454, Dec. 1994.

Crossref

Google Scholar

[3]

Y. Suzuki, K. Odagawa, and T. Abe, "Clocked CMOS calculator circuitry," IEEE J. Solid-State Circuits, vol. SC-8, pp. 462-469, Dec. 1973.

Crossref

Google Scholar

[4]

F. Klass, "Semi-dynamic and dynamic flip-flops with embedded logic," in Symp. VLSI Circuits Dig. Tech. Papers, June 1998, pp. 108-109.

Google Scholar

[5]

H. Partovi et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 138-139.

Google Scholar

[6]

B. Nikolic et al., "Sense amplifier-based flip-flop," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 282-283.

Google Scholar

[7]

M. Hamada et al., "Flip-flop selection technique for power-delay trade-off," in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 270-271.

Google Scholar

[8]

A.G.M. Strollo, E. Napoli, and D. De Caro, "New clock-gating technique for low-power flip-flops," in ISPLED Dig. Tech. Papers, July 2000, pp. 114-119.

Digital Library

Google Scholar

[9]

V. Stojanovic, and V.G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, pp. 536-548, Apr. 1999.

Crossref

Google Scholar

[10]

U. Ko, and P. T. Balsara, "High-performance energy-efficient D flip-flop circuits," IEEE Trans. on VLSI, vol. 8, pp. 94-98, Feb. 2000.

Digital Library

Google Scholar

[11]

I. Sutherland, B. Sproul, and D. Harris, Logical effort: designing fast CMOS circuits, San Francisco, CA: Morgan Kaufmann 1999.

Digital Library

Google Scholar

[12]

S. Heo, R. Krashinsky, and K. Asanovic, "Activity-sensitive flip-flop and latch selection for reduced energy, " Proc. ARVLSI, pp. 59-74, March 2001.

Digital Library

Google Scholar

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Alshaer IBurghoorn GColombier BDeleuze CBeroulle VMaistri P(2024)Cross-layer analysis of clock glitch fault injection while fetching variable-length instructionsJournal of Cryptographic Engineering10.1007/s13389-024-00352-614:2(325-342)Online publication date: 23-Apr-2024
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Index Terms

Analysis and design of low-energy flip-flops
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Information & Contributors

Information

Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01

Sponsor:

SIGDA

ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

Acceptance Rates

ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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https://doi.org/10.3390/app14041657
Alshaer IBurghoorn GColombier BDeleuze CBeroulle VMaistri P(2024)Cross-layer analysis of clock glitch fault injection while fetching variable-length instructionsJournal of Cryptographic Engineering10.1007/s13389-024-00352-614:2(325-342)Online publication date: 23-Apr-2024
https://doi.org/10.1007/s13389-024-00352-6
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Kumar SPanchore MSingh SSingh J(2023)High speed ultra-low-lower lulse-triggered JLFET Flip-FlopModern Physics Letters B10.1142/S021798492450068438:10Online publication date: 19-Oct-2023
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