article

Early analysis tools for system-on-a-chip design

Authors:

J. A. Darringer,

R. A. Bergamaschi,

S. Bhattacharya,

A. Herkersdorf,

Y. ShinAuthors Info & Claims

IBM Journal of Research and Development, Volume 46, Issue 6

Pages 691 - 707

https://doi.org/10.1147/rd.466.0691

Published: 01 November 2002 Publication History

Abstract

The paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic ® Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design.

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Cited By

Bell RSustik MCummings DJackson JKounev SCortellessa VMirandola RLilja DSachs K(2011)Automatic performance model synthesis from hardware verification modelsProceedings of the 2nd ACM/SPEC International Conference on Performance engineering10.1145/1958746.1958816(463-468)Online publication date: 14-Mar-2011
https://dl.acm.org/doi/10.1145/1958746.1958816
Parkhurst JDarringer JGrundmann BHassoun S(2006)From single core to multi-coreProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233516(67-72)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233516
Ohmacht MBergamaschi RBhattacharya SGara AGiampapa MGopalsamy BHaring RHoenicke DKrolak DMarcella JNathanson BSalapura VWazlowski M(2005)Blue Gene/L compute chipIBM Journal of Research and Development10.1147/rd.492.025549:2(255-264)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1147/rd.492.0255
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Published In

cover image IBM Journal of Research and Development

IBM Journal of Research and Development Volume 46, Issue 6

November 2002

157 pages

ISSN:0018-8646

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Publisher

IBM Corp.

United States

Publication History

Published: 01 November 2002

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Cited By

Bell RSustik MCummings DJackson JKounev SCortellessa VMirandola RLilja DSachs K(2011)Automatic performance model synthesis from hardware verification modelsProceedings of the 2nd ACM/SPEC International Conference on Performance engineering10.1145/1958746.1958816(463-468)Online publication date: 14-Mar-2011
https://dl.acm.org/doi/10.1145/1958746.1958816
Parkhurst JDarringer JGrundmann BHassoun S(2006)From single core to multi-coreProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233516(67-72)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233516
Ohmacht MBergamaschi RBhattacharya SGara AGiampapa MGopalsamy BHaring RHoenicke DKrolak DMarcella JNathanson BSalapura VWazlowski M(2005)Blue Gene/L compute chipIBM Journal of Research and Development10.1147/rd.492.025549:2(255-264)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1147/rd.492.0255
Thepayasuwan NDoboli A(2005)Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speedIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.84291013:5(525-538)Online publication date: 1-May-2005
https://dl.acm.org/doi/10.1109/TVLSI.2004.842910
Thepayasuwan NDoboli A(2004)Hardware-Software Co-Design of Resource Constrained Systems on a ChipProceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 710.5555/977399.977952(818-823)Online publication date: 23-Mar-2004
https://dl.acm.org/doi/10.5555/977399.977952
Thepayasuwan NDoboli A(2004)Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on ChipProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969080Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.969080
Jang HKang MLee MChae KLee KShim K(2004)High-Level System Modeling and Architecture Exploration with SystemC on a Network SoCProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969030Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.969030
Bergamaschi RScheffer LMarkov I(2004)Early and accurate analysis of SoCsProceedings of the 2004 international workshop on System level interconnect prediction10.1145/966747.966749(3-6)Online publication date: 14-Feb-2004
https://dl.acm.org/doi/10.1145/966747.966749
Park SLee YShin HButtazzo G(2004)An experimental analysis of the effect of the operating system on memory performance in embedded multimedia computingProceedings of the 4th ACM international conference on Embedded software10.1145/1017753.1017762(26-33)Online publication date: 27-Sep-2004
https://dl.acm.org/doi/10.1145/1017753.1017762
Bergamaschi RShin YDhanwada NBhattacharya SDougherty WNair IDarringer JPaliwal SGupta RNakamura YOrailoglu AChou P(2003)SEASProceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/944645.944687(150-155)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1145/944645.944687
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