article

A very-high output impedance charge pump for low-voltage low-power PLLs

Authors:

L. -F. Tanguay,

M. Sawan,

Y. SavariaAuthors Info & Claims

Microelectronics Journal, Volume 40, Issue 6

Pages 1026 - 1031

https://doi.org/10.1016/j.mejo.2009.03.001

Published: 01 June 2009 Publication History

Abstract

This article presents the design of a high output compliance, very-high output impedance single-ended charge pump implemented using a new low-voltage current mirror. The output current is sampled and a feedback loop forces it to be equal to the desired reference current. This results in a very-high output impedance over a very wide output voltage range, accurate Up/Down current matching, and low transient glitches. The proposed charge pump was implemented using STMicroelectronics 1-V 90-nm CMOS process. Simulations using Spectre show that the Up/Down output currents remain constant and matched within 1% over a charge pump output voltage ranging from 119 to 873mV. Monte Carlo process variations and mismatch simulations indicate that the 1-@s standard deviation between the Up and Down current components is 1.4@mA, or 6.8% of the nominal 20@mA charge pump current at either end of the output voltage range.

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Cited By

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Sivasakthi MRadhika P(2024)A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL applicationAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02225-0118:1(49-66)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1007/s10470-023-02225-0
Samaras DHatzopoulos A(2024)A modular programmable and linear charge pump with low current mismatchAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02183-7118:1(67-76)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1007/s10470-023-02183-7
Ghasemian HBahrami AAbiri ESalehi M(2021)A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS TechnologyCircuits, Systems, and Signal Processing10.1007/s00034-020-01608-240:6(2982-3006)Online publication date: 1-Jun-2021
https://dl.acm.org/doi/10.1007/s00034-020-01608-2
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Published In

Microelectronics Journal Volume 40, Issue 6

June, 2009

161 pages

ISSN:0026-2692

Issue’s Table of Contents

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 June 2009

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Sivasakthi MRadhika P(2024)A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL applicationAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02225-0118:1(49-66)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1007/s10470-023-02225-0
Samaras DHatzopoulos A(2024)A modular programmable and linear charge pump with low current mismatchAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02183-7118:1(67-76)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1007/s10470-023-02183-7
Ghasemian HBahrami AAbiri ESalehi M(2021)A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS TechnologyCircuits, Systems, and Signal Processing10.1007/s00034-020-01608-240:6(2982-3006)Online publication date: 1-Jun-2021
https://dl.acm.org/doi/10.1007/s00034-020-01608-2
Karbalaei Mohammad Ali MHashemipour O(2019)A simple and high performance charge pump based on the self-cascode transistorAnalog Integrated Circuits and Signal Processing10.1007/s10470-019-01478-y100:3(633-638)Online publication date: 1-Sep-2019
https://dl.acm.org/doi/10.1007/s10470-019-01478-y
Manikandan RAmrutur B(2015)A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLsMicroelectronics Journal10.1016/j.mejo.2015.03.00446:6(422-430)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1016/j.mejo.2015.03.004

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A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs

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