research-article

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

Authors:

R.R. Manikandan,

Bharadwaj AmruturAuthors Info & Claims

Microelectronics Journal, Volume 46, Issue 6

Pages 422 - 430

https://doi.org/10.1016/j.mejo.2015.03.004

Published: 01 June 2015 Publication History

Abstract

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 µ m CMOS technology. The frequency synthesizer consumes 8.2mA current from a 1.3V supply voltage and achieves a phase noise of -96.01dBc/Hz @ 1MHz offset from a 2.4GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3µA (0.55%) over the VCO control voltage range of 0.3-1.0V. The closed loop measurements show a minimized static phase error of within 70ps and a 9dB reduction in reference spur level across the PLL output frequency range 2.4-2.5GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations.

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Cited By

Saw SDas PMaiti MMajumder A(2021)A power efficient charge pump circuit configuration for fast locking PLL applicationMicrosystem Technologies10.1007/s00542-018-4037-527:2(479-491)Online publication date: 1-Feb-2021
https://dl.acm.org/doi/10.1007/s00542-018-4037-5
Karbalaei Mohammad Ali MHashemipour O(2019)A simple and high performance charge pump based on the self-cascode transistorAnalog Integrated Circuits and Signal Processing10.1007/s10470-019-01478-y100:3(633-638)Online publication date: 1-Sep-2019
https://dl.acm.org/doi/10.1007/s10470-019-01478-y

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs
1. Hardware
2. Networks
  1. Network types
    1. Ad hoc networks

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cover image Microelectronics Journal

Microelectronics Journal Volume 46, Issue 6

June 2015

149 pages

ISSN:0026-2692

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Copyright © Elsevier Ltd.

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Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 June 2015

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Cited By

Saw SDas PMaiti MMajumder A(2021)A power efficient charge pump circuit configuration for fast locking PLL applicationMicrosystem Technologies10.1007/s00542-018-4037-527:2(479-491)Online publication date: 1-Feb-2021
https://dl.acm.org/doi/10.1007/s00542-018-4037-5
Karbalaei Mohammad Ali MHashemipour O(2019)A simple and high performance charge pump based on the self-cascode transistorAnalog Integrated Circuits and Signal Processing10.1007/s10470-019-01478-y100:3(633-638)Online publication date: 1-Sep-2019
https://dl.acm.org/doi/10.1007/s10470-019-01478-y

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