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A self-tuning cache architecture for embedded systems

Authors:

Chuanjun Zhang,

Frank Vahid,

Roman LyseckyAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 3, Issue 2

Pages 407 - 425

https://doi.org/10.1145/993396.993405

Published: 01 May 2004 Publication History

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Abstract

Memory accesses often account for about half of a microprocessor system's power consumption. Customizing a microprocessor cache's total size, line size, and associativity to a particular program is well known to have tremendous benefits for performance and power. Customizing caches has until recently been restricted to core-based flows, in which a new chip will be fabricated. However, several configurable cache architectures have been proposed recently for use in prefabricated microprocessor platforms. Tuning those caches to a program is still, however, a cumbersome task left for designers, assisted in part by recent computer-aided design (CAD) tuning aids. We propose to move that CAD on-chip, which can greatly increase the acceptance of tunable caches. We introduce on-chip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune the cache to an executing program. Our heuristic seeks not only to reduce the number of configurations that must be examined, but also traverses the search space in a way that minimizes costly cache flushes. By simulating numerous Powerstone and MediaBench benchmarks, we show that such a dynamic self-tuning cache saves on average 40% of total memory access energy over a standard nontuned reference cache.

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Cited By

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Ribeiro LJacobi RJunior Fda Silva JSilva I(2022)Evaluating a Machine Learning-based Approach for Cache Configuration2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789040(1-4)Online publication date: 1-Mar-2022
https://doi.org/10.1109/LASCAS53948.2022.9789040
Navarro OYudi JHoffmann JHernandez HHübner M(2020)A Machine Learning Methodology for Cache Memory Design Based on Dynamic InstructionsACM Transactions on Embedded Computing Systems10.1145/337692019:2(1-20)Online publication date: 11-Mar-2020
https://dl.acm.org/doi/10.1145/3376920
Charles SAhmed AOgras UMishra P(2019)Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPsACM Transactions on Design Automation of Electronic Systems10.1145/335042224:6(1-23)Online publication date: 9-Sep-2019
https://dl.acm.org/doi/10.1145/3350422
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Index Terms

A self-tuning cache architecture for embedded systems
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Reviews

Reviewer: Mehran Rezaei

Tunable cache organization, particularly for embedded systems, is discussed in this paper. Its motivation is that 60 percent of the energy in embedded systems is spent in cache. To reduce such energy consumption-currently one of the main trends in embedded systems research-the paper presents a self-tunable cache that results in a better cache miss rate based on the type of application. "Lower cache miss rate" is synonymous with "less energy consumed," since fewer off-chip accesses are needed. The authors use a reconfigurable cache organization, with three changeable parameters: cache size, associativity, and block size. Way prediction is also supported in their design. They have designed a finite state machine (FSM) that heuristically finds the best configuration for the running application. Based on the FSM result, the cache can be tuned to perform the best in terms of energy consumption. The empirical simulated results show that this approach saves 40 percent of total memory access energy, in comparison with conventional cache. The paper is well written, with a lot of information for readers. The authors state reasonable energy equations, which can be used for further design along the same lines. On average, a good reduction in the energy consumed in the memory system is reported. The authors, however, have not shown the degradation in execution performance as a result of their approach; in fact, they have not shown any execution time data. SimpleScalar tool set, which they used in their experiments, is fully equipped to report cycle execution time, and the authors failed to include such data in their paper. There are techniques that could simply report better cache behavior; I wonder how much benefit this paper's idea would reveal on top of, for example, stream buffers, which are very well behaved in multimedia applications. Online Computing Reviews Service

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 3, Issue 2

May 2004

225 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/993396

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 May 2004

Published in TECS Volume 3, Issue 2

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Cited By

View all

Ribeiro LJacobi RJunior Fda Silva JSilva I(2022)Evaluating a Machine Learning-based Approach for Cache Configuration2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789040(1-4)Online publication date: 1-Mar-2022
https://doi.org/10.1109/LASCAS53948.2022.9789040
Navarro OYudi JHoffmann JHernandez HHübner M(2020)A Machine Learning Methodology for Cache Memory Design Based on Dynamic InstructionsACM Transactions on Embedded Computing Systems10.1145/337692019:2(1-20)Online publication date: 11-Mar-2020
https://dl.acm.org/doi/10.1145/3376920
Charles SAhmed AOgras UMishra P(2019)Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPsACM Transactions on Design Automation of Electronic Systems10.1145/335042224:6(1-23)Online publication date: 9-Sep-2019
https://dl.acm.org/doi/10.1145/3350422
Huang KWang KZheng DZhang XYan X(2018)Access Adaptive and Thread-Aware Cache Partitioning in Multicore SystemsElectronics10.3390/electronics70901727:9(172)Online publication date: 1-Sep-2018
https://doi.org/10.3390/electronics7090172
Badreldin IGordon-Ross AAdegbija TAlsafrjalaniz M(2018)Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00136(719-725)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00136
Sinha MRout SGade SDeb S(2018)Near Threshold Last Level Cache for Energy Efficient Embedded Applications2018 Ninth International Green and Sustainable Computing Conference (IGSC)10.1109/IGCC.2018.8752134(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/IGCC.2018.8752134
Navarro OHuebner M(2018)Runtime Adaptive Cache for the LEON3 ProcessorApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_28(343-354)Online publication date: 8-Apr-2018
https://doi.org/10.1007/978-3-319-78890-6_28
Subramaniyan ARehman SShafique MKumar AHenkel J(2017)Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-coresProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130388(37-42)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130388
Subramaniyan ARehman SShafique MKumar AHenkel J(2017)Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-coresDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7926955(37-42)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7926955
Tang CBodden ESchäfer WDeursen AZisman A(2017)System performance optimization via design and configuration space explorationProceedings of the 2017 11th Joint Meeting on Foundations of Software Engineering10.1145/3106237.3119880(1046-1049)Online publication date: 21-Aug-2017
https://dl.acm.org/doi/10.1145/3106237.3119880
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