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A low power unified cache architecture providing power and performance flexibility (poster session)

Authors:

Afzal Malik,

Bill Moyer,

Dan CermakAuthors Info & Claims

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

Pages 241 - 243

https://doi.org/10.1145/344166.344610

Published: 01 August 2000 Publication History

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Abstract

Advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the devices components. The M7CORE M3 architecture was developed specifically for these embedded applications. To address the growing need for longer battery life and higher performance, an 8-Kbyte, 4-way set-associative, unified (instruction and data) cache with pro-grammable features was added to the M3 core. These features allow the architecture to be optimized based on the applications requirements. In this paper, we focus on the features of the M340 cache sub-system and illustrate the effect on power and perfor-mance through benchmark analysis and actual silicon measure-ments.

References

[1]

J. Circello et al., "The Superscalar Architecture of the MC 68060 '. IEEE Micro, Vol. 15, No. 2, April 1995, pp. 10-21.

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[2]

J. Scott, L. Lee, J. Arends, B. Moyer, "Designing the Low- Power M~CORE Architecture,' Proc. Int 1. Symp. on Computer Architecture Power Driven Microarchitecture Workshop, Barcelona, Spain, July 1998, pp. 145-150.

Google Scholar

[3]

K. Suzuki, T. Arai, N. Kouhei, and I. Kuroda, "V830R/AV: Embedded Multimedia Superscalar RISC Processor'. IEEE Micro, Vol. 18, No. 2, April 1998, pp. 36-47.

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Google Scholar

[4]

M~CORE M340 Reference Manual, Motorola, Inc., 2000.,

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Singh IRaj BKhosla M(2024)Evaluating Reduced-Tag MRAM Architectures for Enhanced Performance in Last-Level Caches2024 First International Conference on Pioneering Developments in Computer Science & Digital Technologies (IC2SDT)10.1109/IC2SDT62152.2024.10696205(291-296)Online publication date: 2-Aug-2024
https://doi.org/10.1109/IC2SDT62152.2024.10696205
Ribeiro LJacobi RJunior Fda Silva JSilva I(2022)Evaluating a Machine Learning-based Approach for Cache Configuration2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789040(1-4)Online publication date: 1-Mar-2022
https://doi.org/10.1109/LASCAS53948.2022.9789040
Charles SAhmed AOgras UMishra P(2019)Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPsACM Transactions on Design Automation of Electronic Systems10.1145/335042224:6(1-23)Online publication date: 9-Sep-2019
https://dl.acm.org/doi/10.1145/3350422
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Index Terms

A low power unified cache architecture providing power and performance flexibility (poster session)
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Hardware validation

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Information & Contributors

Information

Published In

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

August 2000

313 pages

ISBN:1581131909

DOI:10.1145/344166

Editors:
David Blaauw
Motorola, Inc., Austin, TX
,
Christian Enz
CSEM, Maladière, Switzerland
,
Thad Gabara
Lucent Technologies
,
Enrico Macii
Politenico di Torino, Turin, Italy

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 2000

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ISLPED00

Sponsor:

SIGDA
IEEE-CAS

ISLPED00: International Symposium on Low Power Electronic Design

July 25 - 27, 2000

Rapallo, Italy

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Singh IRaj BKhosla M(2024)Evaluating Reduced-Tag MRAM Architectures for Enhanced Performance in Last-Level Caches2024 First International Conference on Pioneering Developments in Computer Science & Digital Technologies (IC2SDT)10.1109/IC2SDT62152.2024.10696205(291-296)Online publication date: 2-Aug-2024
https://doi.org/10.1109/IC2SDT62152.2024.10696205
Ribeiro LJacobi RJunior Fda Silva JSilva I(2022)Evaluating a Machine Learning-based Approach for Cache Configuration2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789040(1-4)Online publication date: 1-Mar-2022
https://doi.org/10.1109/LASCAS53948.2022.9789040
Charles SAhmed AOgras UMishra P(2019)Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPsACM Transactions on Design Automation of Electronic Systems10.1145/335042224:6(1-23)Online publication date: 9-Sep-2019
https://dl.acm.org/doi/10.1145/3350422
Monteiro EGrellert MZatt BBampi S(2019)Energy-aware cache hierarchy assessment targeting HEVC encoder executionJournal of Real-Time Image Processing10.1007/s11554-017-0680-916:5(1695-1715)Online publication date: 1-Oct-2019
https://dl.acm.org/doi/10.1007/s11554-017-0680-9
Alsafrjalani MGordon-Ross A(2018)Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore SystemsComputers10.3390/computers70200257:2(25)Online publication date: 14-Apr-2018
https://doi.org/10.3390/computers7020025
Alsafrjalani MGordon-Ross A(2018)Low Effort Design Space Exploration Methodology for Configurable CachesComputers10.3390/computers70200217:2(21)Online publication date: 27-Mar-2018
https://doi.org/10.3390/computers7020021
Alsafrjalani MAdegbija TChen DHomayoun HTaskin B(2018)TaSaTProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194576(75-80)Online publication date: 30-May-2018
https://dl.acm.org/doi/10.1145/3194554.3194576
Adegbija TGordon-Ross A(2018)PhLock: A Cache Energy Saving Technique Using Phase-Based Cache LockingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.275747726:1(110-121)Online publication date: Jan-2018
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Lattuada MFerrandi FPerrotin M(2018)Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace SystemsIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.26996474:1(3-16)Online publication date: 1-Jan-2018
https://doi.org/10.1109/TMSCS.2017.2699647
Badreldin IGordon-Ross AAdegbija TAlsafrjalaniz M(2018)Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00136(719-725)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00136
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