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Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units

Published: 11 January 2017 Publication History

Abstract

Three-dimensional stacked integrated circuits (3D-SICs) have been expected to overcome the limitations of conventional two-dimensional (2-D) implemented circuits. Since a stacking strategy affects the performance and the power consumption of 3D-SICs, this paper examines two stacking strategies for designing the 3-D stacked floating-point fused multiplyadd (FP-FMA) module which contains four FP-FMA units. Experimental results show that a coarse-grain stacking strategy is suitable for reducing critical path delay of the 3-D stacked FP-FMA module. On the other hand, a fine-grain stacking strategy is suitable for reducing power consumption. The 3-D stacked FP-FMA module which is designed based on a fine-grain stacking strategy achieves an 8.4% critical path delay reduction and an 18% average power reduction compared with the 2-D implementation.

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Cited By

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  • (2019)A Design Scheme for 3-D Stacked CNN Accelerators2019 International 3D Systems Integration Conference (3DIC)10.1109/3DIC48104.2019.9058795(1-4)Online publication date: Oct-2019

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  1. Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units

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    Published In

    cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 44, Issue 4
    HEART '16
    September 2016
    96 pages
    ISSN:0163-5964
    DOI:10.1145/3039902
    Issue’s Table of Contents

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 11 January 2017
    Published in SIGARCH Volume 44, Issue 4

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    Author Tags

    1. 3-D IC stacking
    2. Floating-point unit
    3. Vertical interconnect

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    • (2019)A Design Scheme for 3-D Stacked CNN Accelerators2019 International 3D Systems Integration Conference (3DIC)10.1109/3DIC48104.2019.9058795(1-4)Online publication date: Oct-2019

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