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View all- Tada JTakahashi KEgawa R(2019)A Design Scheme for 3-D Stacked CNN Accelerators2019 International 3D Systems Integration Conference (3DIC)10.1109/3DIC48104.2019.9058795(1-4)Online publication date: Oct-2019
Low power, low cost, and high performance factors dictate the design of many microprocessors targeted to the low-power computing market. The floating-point unit occupies a significant percentage of the silicon area in a microprocessor due its wide data ...
A new floating-point fused multiply-add (FMA) design for the execution of (A × B)+C as a single instruction is presented. The bridge fused multiply-add unit is a design intended to add FMA functionality to existing floating-point coprocessor units by ...
In this paper we propose an architecture for the computation of the double-precision floating-point multiply-add fused (MAF) operation A + (B C) that permits to compute the floating-point addition with lower latency than floating-point multiplication ...
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