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Scalability of 3D-integrated arithmetic units in high-performance microprocessors

Published: 04 June 2007 Publication History

Abstract

Three-Dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance, power, and area benefits of the 3D integration technology. In this paper, we investigate the scalability issues of 3D die-stacked arithmetic units. We explore the behavior of the 3D-integrated arithmetic circuits with increasing issue-width (parallel execution capability), transistor sizing, and temperature. We show that the 3D-integrated units have a lower latency degradation and lower rate of increase in energy consumption than the planar circuits with increasing issue-widths and operating temperatures. We demonstrate that the 3D-integrated circuits have less sensitivity to transistor sizing than the planar circuits.

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Cited By

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  • (2017)Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add UnitsACM SIGARCH Computer Architecture News10.1145/3039902.303991444:4(62-67)Online publication date: 11-Jan-2017
  • (2015)Interconnect-Memory Challenges for Multi-chip, Silicon Interposer SystemsProceedings of the 2015 International Symposium on Memory Systems10.1145/2818950.2818951(3-10)Online publication date: 5-Oct-2015
  • (2014)Performance evaluation of 3-D stacked 32-bit parallel multipliersACM SIGARCH Computer Architecture News10.1145/2641361.264137641:5(89-94)Online publication date: 18-Jun-2014
  • Show More Cited By

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    cover image ACM Conferences
    DAC '07: Proceedings of the 44th annual Design Automation Conference
    June 2007
    1016 pages
    ISBN:9781595936271
    DOI:10.1145/1278480
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 04 June 2007

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    Author Tags

    1. die-stacked 3D integration
    2. issue-width
    3. scalability

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    View all
    • (2017)Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add UnitsACM SIGARCH Computer Architecture News10.1145/3039902.303991444:4(62-67)Online publication date: 11-Jan-2017
    • (2015)Interconnect-Memory Challenges for Multi-chip, Silicon Interposer SystemsProceedings of the 2015 International Symposium on Memory Systems10.1145/2818950.2818951(3-10)Online publication date: 5-Oct-2015
    • (2014)Performance evaluation of 3-D stacked 32-bit parallel multipliersACM SIGARCH Computer Architecture News10.1145/2641361.264137641:5(89-94)Online publication date: 18-Jun-2014
    • (2013)Design of a 3-D stacked floating-point adder2013 IEEE International 3D Systems Integration Conference (3DIC)10.1109/3DIC.2013.6702390(1-4)Online publication date: Oct-2013
    • (2012)A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International10.1109/3DIC.2012.6263031(1-6)Online publication date: Jan-2012
    • (2012)Exploring a Design Space of 3-D Stacked Vector ProcessorsSustained Simulation Performance 201210.1007/978-3-642-32454-3_4(35-49)Online publication date: 27-Aug-2012
    • (2010)Processor Architecture Design Using 3D Integration TechnologyProceedings of the 2010 23rd International Conference on VLSI Design10.1109/VLSI.Design.2010.60(446-451)Online publication date: 3-Jan-2010
    • (2010)Performance analysis of 3-D monolithic integrated circuits2010 IEEE International 3D Systems Integration Conference (3DIC)10.1109/3DIC.2010.5751465(1-4)Online publication date: Nov-2010
    • (2009)Perspectives and issues in 3D-IC from designers' point of view2009 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2009.5117688(73-76)Online publication date: May-2009
    • (2009)Evaluation of fine grain 3-D integrated arithmetic units2009 IEEE International Conference on 3D System Integration10.1109/3DIC.2009.5306566(1-8)Online publication date: Sep-2009
    • Show More Cited By

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