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Modulo scheduling for a fully-distributed clustered VLIW architecture

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Jesús Sánchez,

Antonio GonzálezAuthors Info & Claims

MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Pages 124 - 133

https://doi.org/10.1145/360128.360142

Published: 01 December 2000 Publication History

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Cited By

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Ko YKim SKim HLee K(2021)Selective Code Duplication for Soft Error Protection on VLIW ArchitecturesElectronics10.3390/electronics1015183510:15(1835)Online publication date: 30-Jul-2021
https://doi.org/10.3390/electronics10151835
Kim WChoi YPark H(2013)Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architecturesACM Transactions on Architecture and Code Optimization10.1145/2541228.255531410:4(1-24)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2541228.2555314
Govindarajan R(2010)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420040579.ch17Online publication date: 7-Mar-2010
https://doi.org/10.1201/9781420040579.ch17
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Published In

MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

December 2000

357 pages

ISBN:1581131968

DOI:10.1145/360128

Chairmen:
Andrew Wolfe
S3 Incorporated
,
Michael Schlansker
Hewlett-Packard

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 December 2000

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MICRO00: 33rd Annual International Symposium on Microarchitecture

California, Monterey, USA

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MICRO 33 Paper Acceptance Rate 31 of 110 submissions, 28%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

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Ko YKim SKim HLee K(2021)Selective Code Duplication for Soft Error Protection on VLIW ArchitecturesElectronics10.3390/electronics1015183510:15(1835)Online publication date: 30-Jul-2021
https://doi.org/10.3390/electronics10151835
Kim WChoi YPark H(2013)Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architecturesACM Transactions on Architecture and Code Optimization10.1145/2541228.255531410:4(1-24)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2541228.2555314
Govindarajan R(2010)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420040579.ch17Online publication date: 7-Mar-2010
https://doi.org/10.1201/9781420040579.ch17
Catthoor FRaghavan PLambrechts AJayapala MKritikakou AAbsar JCatthoor FRaghavan PLambrechts AJayapala MKritikakou AAbsar J(2010)An Asymmetrical Register File: The VWRUltra-Low Energy Domain-Specific Instruction-Set Processors10.1007/978-90-481-9528-2_8(199-222)Online publication date: 3-Jul-2010
https://doi.org/10.1007/978-90-481-9528-2_8
Zhao YXue CLi MHu BWakabayashi K(2009)Energy-aware register file re-partitioning for clustered VLIW architecturesProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509813(805-810)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509813
Taylor MLee WMiller JWentzlaff DBratt IGreenwald BHoffmann HJohnson PKim JPsota JSaraf AShnidman NStrumpen VFrank MAmarasinghe SAgarwal A(2009)Tiled Multicore ProcessorsMulticore Processors and Systems10.1007/978-1-4419-0263-4_1(1-33)Online publication date: 3-Aug-2009
https://doi.org/10.1007/978-1-4419-0263-4_1
Park HFan KMahlke SOh TKim HKim HMoshovos ATarditi DOlukotun K(2008)Edge-centric modulo scheduling for coarse-grained reconfigurable architecturesProceedings of the 17th international conference on Parallel architectures and compilation techniques10.1145/1454115.1454140(166-176)Online publication date: 25-Oct-2008
https://dl.acm.org/doi/10.1145/1454115.1454140
Kudlur MMahlke S(2008)Orchestrating the execution of stream programs on multicore platformsACM SIGPLAN Notices10.1145/1379022.137559643:6(114-124)Online publication date: 7-Jun-2008
https://dl.acm.org/doi/10.1145/1379022.1375596
Kudlur MMahlke SGupta RAmarasinghe S(2008)Orchestrating the execution of stream programs on multicore platformsProceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/1375581.1375596(114-124)Online publication date: 7-Jun-2008
https://dl.acm.org/doi/10.1145/1375581.1375596
Fan KPark HKudlur MMahlke SSoffa MDuesterwald E(2008)Modulo scheduling for highly customized datapaths to increase hardware reusabilityProceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1356058.1356075(124-133)Online publication date: 6-Apr-2008
https://dl.acm.org/doi/10.1145/1356058.1356075
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Pragmatic integrated scheduling for clustered VLIW architectures

Instruction scheduling and fetch mechanisms for clustered vliw processors

Modulo scheduling for the TMS320C6x VLIW DSP architecture