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Partitioned register files for VLIWs: a preliminary analysis of tradeoffs

Published: 10 December 1992 Publication History
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References

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A. Abnous, J. Gray, A. Naylor, and N. Bagherzadeh. VIPER: a 25-MHz, 100-MIPS Peak VLIW Microprocessor, TR 92-78. ECE Tech. Rep. no. 92-78, University of California, Irvine, 1992.
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M.L. Anido, D.J. Allerton, and E.J. Zaluska. A three-port/three-access register file for concurrent processing and I/O communication in a RISC like graphics engine. In The 16th Annual International Symposium on Computer Architecture, page 354, 1989.
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Andrea Capitanio, Nikil Dutt, and Alexandru Nicolau. An Improved Partitioning Algorithm. Technical Report 92-57, UC Irvine, ICS Dept., 1992.
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Andrea Capitanio, Nikil Dutt, and Alexandru Nicolau. Design Considerations for Limited Connectivity VLIW Architectures. Technical Report 92-59, UC Irvine, ICS Dept., 1992.
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Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papwoth, and Paul K. Rodman. A VLIW Architecture for a Trace Sceduling Compiler. IEEE Trans. on Computers, 37(8):967, August 1988.
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K. Ebcioglu. Some Design Ideas for a VLIW Architecture for Sequential Natured Software. In Parallel Processing, Proc. IFIP WG 10.3 Working Conference on Parallel Processing, 1988.
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Jonh R. Ellis. Bulldog: A compler for VLIW Architectures. PhD thesis, Yale University, Dept. of Computer Science, 1985.
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Hank Walker CMU, Personal Communication, 1992.
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C.M. Fidduccia and R.M. Mattheyses. A Linear Time Heuristic for Improving Network Partitioning. In 19th Design Automation Conference, page 175, 1982.
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J. A. Fisher. Trace Scheduling: A technique for Global Microcode Compaction. IEEE Trans. on Computers, 30:478, July 1981.
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J. A. Fisher and B. R. Rau. Instruction Parallel Processing. Science, (253):1233- 1241, September 1991.
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R. D. Jolly. A 9-ns, 1.4-Gigabyte/s, 17-Ported CMOS Register File. IEEE Journal of Solid State Circuit, vol. 26(no.10):1407, 1991.
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C.H. Lee, C.I. Park, and M. Kim. Efficient Algorithm for graph partitioning problem using a problem transformation method. Computer Aided Design, 21(10):611, December 1989.
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S. Lee and J.K. Aggarwal. A Mapping Strategy for Parallel Processing. IEEE Trans. on Computers, C-36(4), April 1987.
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Alexandru Nicolau. Uniform Parallelism Exploitation in Ordinary Programs. Proceedings of the 1985 International Conference on Parallel Processing, 1985.
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Roni Potasman. Percolation Based Compiling for Evaluation of Parallelism and Hardware Design Trade-Offs. PhD thesis, University of California, Irvine. Dept. of Information and Computer Science, 1992.

Cited By

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  • (2017)The CUREACM Transactions on Embedded Computing Systems10.1145/312652716:5s(1-19)Online publication date: 27-Sep-2017
  • (2014)Shared-port register file architecture for low-energy VLIW processorsACM Transactions on Architecture and Code Optimization10.1145/253339711:1(1-32)Online publication date: 1-Feb-2014
  • (2014)Achieving spilling-friendly register file assignment for highly distributed register filesThe Journal of Supercomputing10.1007/s11227-014-1181-269:3(1342-1362)Online publication date: 1-Sep-2014
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cover image ACM Conferences
MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture
December 1992
301 pages
ISBN:0818631759

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IEEE Computer Society Press

Washington, DC, United States

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Published: 10 December 1992

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Cited By

View all
  • (2017)The CUREACM Transactions on Embedded Computing Systems10.1145/312652716:5s(1-19)Online publication date: 27-Sep-2017
  • (2014)Shared-port register file architecture for low-energy VLIW processorsACM Transactions on Architecture and Code Optimization10.1145/253339711:1(1-32)Online publication date: 1-Feb-2014
  • (2014)Achieving spilling-friendly register file assignment for highly distributed register filesThe Journal of Supercomputing10.1007/s11227-014-1181-269:3(1342-1362)Online publication date: 1-Sep-2014
  • (2013)CAeSaRProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555738(1-10)Online publication date: 29-Sep-2013
  • (2013)LUCASACM SIGPLAN Notices10.1145/2499369.246556548:5(45-54)Online publication date: 20-Jun-2013
  • (2013)LUCASProceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2491899.2465565(45-54)Online publication date: 20-Jun-2013
  • (2013)LUCASProceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2465554.2465565(45-54)Online publication date: 20-Jun-2013
  • (2013)Joint variable partitioning and bank selection instruction optimization for partitioned memory architecturesACM Transactions on Embedded Computing Systems10.1145/2442116.244212612:3(1-27)Online publication date: 8-Apr-2013
  • (2012)SIMD defragmenterACM SIGPLAN Notices10.1145/2248487.215101447:4(363-374)Online publication date: 3-Mar-2012
  • (2012)SIMD defragmenterACM SIGARCH Computer Architecture News10.1145/2189750.215101440:1(363-374)Online publication date: 3-Mar-2012
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