Browse Theses

When it comes to performance, modern computer design has become a well structured art which starts with instruction sets that maximize opportunities for concurrency, follows through with fast organizational techniques such as pipelining and super scalar execution, and ends with clever macro and circuit designs that are based on inherently fast CMOS fabrication technologies. When it comes to low power, however, exactly the opposite is true. Current techniques start with lowering supply voltages and making process changes to minimize capacitance, followed by some relatively simple techniques for minimizing power for particular logic macros, and then utilizing relatively ad hoc techniques, such as ‘sleep modes’, at higher levels. This work attempts to reverse this by bringing the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power- optimization of high-performance microprocessors at the microarchitecture level. In particular, our work explores solutions to the problem that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed, or will be heavily consumed in next- generation processors. This involves developing energy models for structures where power grows with increasing issue width, such as Register File, Issue Window, Memory Disambiguation Unit, etc. Then, a multicluster microarchitecture is developed that reduces energy in the identified critical design points, with minimal performance impact, Detailed simulation of the baseline and proposed multicluster architectures has been performed, optimizing both for the energy-delay metric. A comparison of the two microarchitectures, both optimized for energy efficiency, shows that the multicluster architecture is potentially up to twice as energy efficient for wide issue processors, with an advantage that grows with the issue width. Conversely, at the same power dissipation level the new multicluster architecture supports configurations with measurably higher performance than equivalent conventional designs.