Introduction to the Special Issue on Machine Learning for CAD/EDA
Authors: 
Yibo Lin, 
Avi Ziv, Haoxing RenAuthors Info & Claims
Article No.: 14, Pages 1 - 2
Recent advances in machine learning (ML) have brought revolutions for a variety of applications like computer vision, recommendation systems, and robotics. Many researches have been exploring the applications of ML to CAD/EDA problems. However, the design processes in the CAD flow present challenges to achieve high accuracy, generality, and efficiency. Compared to traditional ML applications such as computer vision, parallel advances in ML and CAD are often required to achieve effectiveness in the design processes. This special issue on Machine Learning for CAD/EDA focuses on concepts and methods for applying machine learning techniques to improve design performance and speed up design closure in the CAD flow.
The idea for this special issue originated at a workshop on “Machine Learning for CAD (MLCAD)” held in 2021. In response to our call for papers released in early 2021, we received 22 submissions, of which 17 were selected for an accelerated review and revision process. This special issue collects the final 13 accepted articles covering a wide range of topics at various perspectives in the CAD flow, including surveys on ML for CAD applications, ML for analog design optimization, ML for digital design optimization, and ML for design analysis. The articles presented in this special issue are aimed at providing a systematic perspective beyond a single isolated domain to stimulate discussion and development of innovative ML approaches in CAD applications.
The articles in the special issue fall into four categories.
Category MLCAD Surveys contains two articles.
(1)
The first article, “A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications”, presents a comprehensive review of the existing works linking the CAD flow and graph neural networks. This article analyzes the practical implications, outcomes, and challenges in applying graph neural networks to CAD problems.
(2)
The second article, “A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation”, reviews the state-of-the-art ML techniques for security-aware circuit design/optimization, summarizes the engineering challenges, and suggests future research directions.
Category ML for Analog Design Optimization contains three articles leveraging ML techniques to optimize analog circuits.
(1)
The first article, “Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search”, proposes to exploit upper-confidence-bound-tree-based searching learning to automate the exploration of topology space and design specifications in power converter circuit design.
(2)
The second article, “Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization”, proposes an ML-assisted prediction model to enhance an evolutionary algorithm for the transistor sizing problem in low-voltage analog circuits.
(3)
The third article, “Performance Driven Wire Sizing for Analog Integrated Circuits”, leverages a graph neural network to predict performance of analog circuits and Bayesian optimization to explore proper wire sizes that can achieve best performance.
Category ML for Digital Design Optimization contains three articles leveraging ML techniques to optimize digital circuits.
The first article, “Machine-Learning-Driven Architectural Selection of Adders and Multipliers in Logic Synthesis”, proposes to automatically search architectures of adders and multipliers with multi-perception neural networks.
The second article, “GraphPlanner: Floorplanning with Graph Neutral Network ”, exploits graph neural networks to generate initial macro locations for placement. This article also proposes a synthetic data generation method to augment the dataset for training ML models.
The third article, “Efficient Test Chip Design via Smart Computation ”, accelerates the logic test chip design process by utilizing random forest classification for design exploration and formulates an integer programming for design optimization.
Category ML for Design Analysis contains five articles leveraging ML techniques for design analysis.
The first article, “Learning-based Phase-aware Multi-core CPU Workload Forecasting”, proposes a kmeans clustering with a support vector machine based model for workload phase classification and prediction.
The second article, “Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs”, presents a fast estimation of on-chip resources at register transfer level based on various ML models.
The third article, “Graph Neural Networks for High-Level Synthesis Design Space Explorations”, proposes an approach to jointly predict the acceleration performance and hardware costs of a synthesized behavioral specification given optimization directives for design space exploration in high-level synthesis.
The fourth article, “Training PPA Models for Embedded Memories On a Low Data Diet”, proposes to predict the performance of embedded memories by combining supervised learning and transfer learning techniques.
The fifth article, “BoA-PTA, an Error-Free Bayesian Optimization Accelerated PTA Solver for SPICE Simulation”, accelerates the pseudo transient analysis by Bayesian optimization, which can be used to speed up ongoing repeated simulations or to improve new simulations of completely different circuits.
Yibo Lin
Peking University, China
Avi Ziv
IBM Research, Israel
Haoxing Ren
NVIDIA Corp., United States
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March 2023
409 pages
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Association for Computing Machinery
New York, NY, United States
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Published: 31 March 2023
Published in TODAES Volume 28, Issue 2
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