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On the generation of multiplexer circuits for pass transistor logic

Authors:

Christoph Scholl,

Bernd BeckerAuthors Info & Claims

DATE '00: Proceedings of the conference on Design, automation and test in Europe

Pages 372 - 379

https://doi.org/10.1145/343647.343800

Published: 01 January 2000 Publication History

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Ovy SIslam Romel MXiao YXu YNi KGeorge S(2024)Compact Multiplexer Design with Multi-threshold Ferroelectric FETs2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00142(735-739)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00142
Imran MHan HKim JKwon TChung JYang J(2020)Virtualization-Based Efficient TSV Repair for 3-D Integrated CircuitsIEEE Access10.1109/ACCESS.2019.29402118(42231-42242)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2019.2940211
da Rosa LReis ARibas RMarques FSchneider FPetraglia APedroni VCauwenberghs G(2007)A comparative study of CMOS gates with minimum transistor stacksProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284511(93-98)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284511
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Index Terms

On the generation of multiplexer circuits for pass transistor logic
1. Hardware

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DATE '00: Proceedings of the conference on Design, automation and test in Europe

January 2000

707 pages

ISBN:1581132441

DOI:10.1145/343647

Chairman:
Ivo Bolsens
IMEC, Leuven, Belgium

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Published: 01 January 2000

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DATE00: Design Automation and Test in Europe

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Cited By

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Ovy SIslam Romel MXiao YXu YNi KGeorge S(2024)Compact Multiplexer Design with Multi-threshold Ferroelectric FETs2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00142(735-739)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00142
Imran MHan HKim JKwon TChung JYang J(2020)Virtualization-Based Efficient TSV Repair for 3-D Integrated CircuitsIEEE Access10.1109/ACCESS.2019.29402118(42231-42242)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2019.2940211
da Rosa LReis ARibas RMarques FSchneider FPetraglia APedroni VCauwenberghs G(2007)A comparative study of CMOS gates with minimum transistor stacksProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284511(93-98)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284511
da Rosa Junior LMarques FCardoso TRibas RSapatnekar SReis ACoelho CJacobi RBecker J(2006)Fast disjoint transistor networks from BDDsProceedings of the 19th annual symposium on Integrated circuits and systems design10.1145/1150343.1150381(137-142)Online publication date: 28-Aug-2006
https://dl.acm.org/doi/10.1145/1150343.1150381
Ebendt RDrechsler R(2006)Exact minimisation of path-related objective functions for binary decision diagramsIEE Proceedings - Computers and Digital Techniques10.1049/ip-cdt:20050181153:4(231)Online publication date: 2006
https://doi.org/10.1049/ip-cdt:20050181
Shelar RSapatnekar S(2005)BDD decomposition for delay oriented pass transistor logic synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.85360113:8(957-970)Online publication date: 1-Aug-2005
https://dl.acm.org/doi/10.1109/TVLSI.2005.853601
Butler JSasao TMatsuura M(2005)Average Path Length of Binary Decision DiagramsIEEE Transactions on Computers10.1109/TC.2005.13754:9(1041-1053)Online publication date: 1-Sep-2005
https://dl.acm.org/doi/10.1109/TC.2005.137
Schneider FRibas RSapatnekar SReis A(2005)Exact lower bound for the number of switches in series to implement a combinational logic cellProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.51(357-362)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.51
Ebendt RGünther WDrechsler RImai M(2004)Minimization of the expected path length in BDDs based on local changesProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015321(865-870)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015321
Aguirre ACoello Coello C(2004)Using genetic programing and multiplexers for the synthesis of logic circuitsEngineering Optimization10.1080/0305215041000168650336:4(491-511)Online publication date: Aug-2004
https://doi.org/10.1080/03052150410001686503
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