Article

Free access

Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits

Authors:

F. SomenziAuthors Info & Claims

ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Pages 235 - 241

https://doi.org/10.1145/288548.288619

Published: 01 November 1998 Publication History

PDF eReader

References

[1]

R. E. Bryant, "Graph-Based Algorithm for Boolean FUnction Manipulation," IEEE ~'ans. on Computers, Vol. C-35, No. 8, pp. 79-85, August 1986.

Digital Library

Google Scholar

[2]

K. Yano, Y. Sasaki, K. 19ikino, K. Seki, "Top-Down Pass- Transistor Logic," IEEE Journal of Solid-Stat~ Circuits, Vol. 31, No. 6, pp. 792-803, June 1996.

Crossref

Google Scholar

[3]

K. Konishi, S. Kishimoto, B-Y. Lee, H. Tanaka, K. Taki, "A Logic Synthesis System for the Pass Transistor Logic SPL," SASIJ~fI'96, pp. 32-39, Fukuoka, Japan, November 1996.

Google Scholar

[4]

M. Tachlbana, "Heuristic Algorithm for FBDD Node Minimization with Application to Pass-Translstor Logic and DCVS Synthesis," SASI~fP96, pp. 96-101, Fukuoka, Japan, November 1996.

Google Scholar

[5]

V. Bertacco, S. Minato, P. Verplaetse, L. Benini, G. De Micheli) "Decision Diagrams and Pass Transistor Logic Synthesis/' IWLS-97, Paper 3.1, Lake Tahoe, CA, May 1997.

Google Scholar

[6]

P. Buch, A. Narayan, A. 1%. Newton, A. L. Sangiovanni- Vlncentelli, "Logic Synthesis for Large Pass Transistor Networks," ICCAD-97, pp. 663-670, San Jose, CA, November 1997.

Digital Library

Google Scholar

[7]

A. Kuehlmann, F. Krohm, "Combinational Verification Using Cuts and Heaps," DAG-J~, pp. 263-268, Anaheim, CA, June 1997.

Digital Library

Google Scholar

[8]

N. Weste, K. Eshraghian, Principles o} GMOS VLSI Design: A Systems Perspective)Addison-Wesley) 1992.

Digital Library

Google Scholar

[9]

M. Held, I%. M. Karp, "A Dynamic Programming Approach to Sequencing Problems," SIAJ~{ .Tourna~ Vo}. 10 No. 1, pp. 196- 210, 1962.

Crossref

Google Scholar

[10]

R. 1%udell, Logic S~Inthesis for VLSI Design, Ph.D. Dissertation, Tech. Rep. UCB/ERL M89/49, Dept. of EECS, University of California, Berkeley, CA, April 1989.

Digital Library

Google Scholar

[11]

E. M. Sentovich, K. J. Singh, C. W. Moon, H. Savoij, 1%. K. Brayton, A. Sangiovanni-Vincentelli, "Sequential Circuits Design Using Synthesis and Optimization," ICCD-92, pp. 328- 333, Cambridge, MA, October 1992.

Digital Library

Google Scholar

[12]

F. Somenzl, GUDD: Univer~it9 of Colorado Dec~J~.on Diagram Pacicage, Release 2.1.2, Tech. Rep., Dept. of ECE, University of Colorado, Boulder, CO, April 1997.

Google Scholar

[13]

A. Grenier, F. Pecheux, ALLIANCE: A Complete Set of CAD Tools for Teaching VLSI Design, Tech. 1%ep., Laboratoire MASI/CAO-VLSI, Universit~ Pierre e Marie Curie, Pads, France, 1993.

Google Scholar

[14]

F. Brglez, H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," ISGAS-85, pp. 785-794, Kyoto, Japan, June 1985.

Google Scholar

Cited By

View all

Macii ECalimera AMacii APoncino M(2017) Logic Synthesis of CMOS Circuits and Beyond Nanoelectronics10.1002/9783527800728.ch14(331-362)Online publication date: 7-Apr-2017
https://doi.org/10.1002/9783527800728.ch14
Jabeur KYakymets NO'Connor ILe Beux S(2011)Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cellsProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2011.5941499(162-168)Online publication date: 8-Jun-2011
https://dl.acm.org/doi/10.1109/NANOARCH.2011.5941499
Ebendt RDrechsler R(2009)Weighted A∗ search -- unifying view and applicationArtificial Intelligence10.1016/j.artint.2009.06.004173:14(1310-1342)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1016/j.artint.2009.06.004
Show More Cited By

Index Terms

Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits

Recommendations

Logic synthesis for large pass transistor circuits
ICCAD '97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. In this work, we motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for ...
Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic
DSD '04: Proceedings of the Digital System Design, EUROMICRO Systems

This paper presents the realization of multiple-valued flip-flops (MVFF) using Pass Transistor logic. Realization of MVFF has been discussed by many authors. The existing techniques are mainly extensions of binary flip-flops, based on CMOS or TTL logic. ...
Synthesis of skewed logic circuits

Skewed logic circuits belong to a noise-tolerant high-performance static circuit family. Skewed logic circuits can achieve performance comparable to that of Domino logic circuits but with much lower power consumption. Two factors contribute to the ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

November 1998

704 pages

ISBN:1581130082

DOI:10.1145/288548

Chairman:
Hiroto Yasuura
Kyushu Univ., Fukuoka, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 November 1998

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ICCAD '98

Sponsor:

IEEE-EDS
SIGDA
IEEE-CAS
IEEE-CS

ICCAD '98: International Conference on Computer-Aided Design - 1998

November 8 - 12, 1998

California, San Jose, USA

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
293
Total Downloads

Downloads (Last 12 months)35
Downloads (Last 6 weeks)4

Reflects downloads up to 16 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Macii ECalimera AMacii APoncino M(2017) Logic Synthesis of CMOS Circuits and Beyond Nanoelectronics10.1002/9783527800728.ch14(331-362)Online publication date: 7-Apr-2017
https://doi.org/10.1002/9783527800728.ch14
Jabeur KYakymets NO'Connor ILe Beux S(2011)Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cellsProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2011.5941499(162-168)Online publication date: 8-Jun-2011
https://dl.acm.org/doi/10.1109/NANOARCH.2011.5941499
Ebendt RDrechsler R(2009)Weighted A∗ search -- unifying view and applicationArtificial Intelligence10.1016/j.artint.2009.06.004173:14(1310-1342)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1016/j.artint.2009.06.004
Drechsler NHilgemeier MFey GDrechsler R(2004)Disjoint Sum of Product Minimization by Evolutionary AlgorithmsApplications of Evolutionary Computing10.1007/978-3-540-24653-4_21(198-207)Online publication date: 2004
https://doi.org/10.1007/978-3-540-24653-4_21
Ebendt RGunther WDrechsler R(2003)Combination of Lower Bounds in Exact BDD MinimizationProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022816Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022816
Shelar RSapatnekar SErnst R(2001)Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuitsProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603188(449-452)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603188
Macchiarulo LBenini LMacii E(2001)On-the-fly layout generation for PTL macrocellsProceedings of the conference on Design, automation and test in Europe10.5555/367072.367391(546-551)Online publication date: 13-Mar-2001
https://dl.acm.org/doi/10.5555/367072.367391
Chatzigeorgiou ANikolaidis S(2001)Modelling the operation of pass transistor and CPL gatesInternational Journal of Electronics10.1080/0020721011006618588:9(977-1000)Online publication date: Sep-2001
https://doi.org/10.1080/00207210110066185
Scholl CBecker BBolsens I(2000)On the generation of multiplexer circuits for pass transistor logicProceedings of the conference on Design, automation and test in Europe10.1145/343647.343800(372-379)Online publication date: 1-Jan-2000
https://dl.acm.org/doi/10.1145/343647.343800
Guerra e Silva LSilveira LMarques-Silva J(1999)Algorithms for solving Boolean satisfiability in combinational circuitsProceedings of the conference on Design, automation and test in Europe10.1145/307418.307557(107-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307557

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Logic synthesis for large pass transistor circuits

Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic

Synthesis of skewed logic circuits