research-article

Efficient Parasitic-aware g^m/I^D-based Hybrid Sizing Methodology for Analog and RF Integrated Circuits

Authors:

Lihong ZhangAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 26, Issue 2

Article No.: 10, Pages 1 - 31

https://doi.org/10.1145/3416946

Published: 28 October 2020 Publication History

Abstract

As the primary second-order effect, parasitic issues have to be seriously addressed when synthesizing high-performance analog and RF integrated circuits (ICs). In this article, a two-phase hybrid sizing methodology for analog and RF ICs is proposed to take into account parasitic effect in the early design stage. It involves symbolic modeling and mixed-integer nonlinear programming (MINLP) in the first phase, and a many-objective evolutionary algorithm (many-OEA)-based sizing refiner in the second phase. With the aid of our proposed current density factor and piecewise curve fitting technique, the g^m/I^D concept, which is typically utilized to solve the analog circuit design problem, can provide theoretical support to our accurate symbolic modeling. Thus, the intrinsic and interconnect parasitics can be accurately considered in our work with moderate modeling effort. A variety of electrical, geometric, and parasitic (including parasitic mismatch) constraints can be conveniently integrated into our MINLP problem formulation. Moreover, numerical simulations are embedded into the many-OEA-based sizing phase, which is able to tackle floorplan co-optimization. With such dynamic floorplan variation, the parasitics accuracy can be sustained along the evolution. The experimental results demonstrate high efficacy of our proposed parasitic-aware hybrid sizing methodology.

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Cited By

Arani MShahidi RZhang L(2024)A State-of-the-Art Survey on Advanced Electromagnetic Design: A Machine-Learning PerspectiveIEEE Open Journal of Antennas and Propagation10.1109/OJAP.2024.34126095:4(1077-1094)Online publication date: Aug-2024
https://doi.org/10.1109/OJAP.2024.3412609
Nasiri HLi CZhang L(2024)Reinforcement-Learning-Based Successive Approximation Algorithm2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558578(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558578
Xie QLi ZShi G(2023)Design Space Exploration of Multi-Stage Op Amps by Symbolic Modeling and gm/ID Sampling2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218716(40-45)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218716
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Index Terms

Efficient Parasitic-aware g^m/I^D-based Hybrid Sizing Methodology for Analog and RF Integrated Circuits
1. Hardware
  1. Electronic design automation
    1. Methodologies for EDA

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 26, Issue 2

March 2021

220 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3430836

Editor:
X. Sharon Hu
University of Notre Dame, USA

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Copyright © 2020 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 October 2020

Accepted: 01 August 2020

Revised: 01 July 2020

Received: 01 April 2019

Published in TODAES Volume 26, Issue 2

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Cited By

Arani MShahidi RZhang L(2024)A State-of-the-Art Survey on Advanced Electromagnetic Design: A Machine-Learning PerspectiveIEEE Open Journal of Antennas and Propagation10.1109/OJAP.2024.34126095:4(1077-1094)Online publication date: Aug-2024
https://doi.org/10.1109/OJAP.2024.3412609
Nasiri HLi CZhang L(2024)Reinforcement-Learning-Based Successive Approximation Algorithm2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558578(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558578
Xie QLi ZShi G(2023)Design Space Exploration of Multi-Stage Op Amps by Symbolic Modeling and gm/ID Sampling2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218716(40-45)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218716
Li YLin YMadhusudan MSharma ASapatnekar SHarjani RHu J(2022)Performance-driven Wire Sizing for Analog Integrated CircuitsACM Transactions on Design Automation of Electronic Systems10.1145/355954228:2(1-23)Online publication date: 24-Dec-2022
https://dl.acm.org/doi/10.1145/3559542

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