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The validity of retiming sequential circuits

Authors:

Vigyan Singhal,

Carl Pixley,

Richard L. Rudell,

Robert K. BraytonAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 316 - 321

https://doi.org/10.1145/217474.217548

Published: 01 January 1995 Publication History

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References

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Cited By

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Zhou H(2008)A new efficient retiming algorithm derived by formal manipulationACM Transactions on Design Automation of Electronic Systems10.1145/1297666.129767313:1(1-19)Online publication date: 6-Feb-2008
https://dl.acm.org/doi/10.1145/1297666.1297673
Baumgartner JMony HParuthi VKanzelman RJanssen G(2006)Scalable Sequential Equivalence Checking across Arbitrary Design Transformations2006 International Conference on Computer Design10.1109/ICCD.2006.4380826(259-266)Online publication date: Oct-2006
https://doi.org/10.1109/ICCD.2006.4380826
Jiang J(2005)On some transformation invariants under retiming and resynthesisProceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems10.1007/978-3-540-31980-1_27(413-428)Online publication date: 4-Apr-2005
https://dl.acm.org/doi/10.1007/978-3-540-31980-1_27
Show More Cited By

Index Terms

The validity of retiming sequential circuits
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
  2. Integrated circuits
    1. Logic circuits
      1. Sequential circuits

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Retiming is used to optimize logic and improve the speed of operation in sequential circuits keeping the circuit behavior unchanged. In this paper, we show with various examples that retiming affects redundancy of faults. It may change an operationally ...

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 January 1995

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June 12 - 16, 1995

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Zhou H(2008)A new efficient retiming algorithm derived by formal manipulationACM Transactions on Design Automation of Electronic Systems10.1145/1297666.129767313:1(1-19)Online publication date: 6-Feb-2008
https://dl.acm.org/doi/10.1145/1297666.1297673
Baumgartner JMony HParuthi VKanzelman RJanssen G(2006)Scalable Sequential Equivalence Checking across Arbitrary Design Transformations2006 International Conference on Computer Design10.1109/ICCD.2006.4380826(259-266)Online publication date: Oct-2006
https://doi.org/10.1109/ICCD.2006.4380826
Jiang J(2005)On some transformation invariants under retiming and resynthesisProceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems10.1007/978-3-540-31980-1_27(413-428)Online publication date: 4-Apr-2005
https://dl.acm.org/doi/10.1007/978-3-540-31980-1_27
Mneimneh MSakallah KMoondanos JImai M(2004)Preserving synchronizing sequences of sequential circuits after retimingProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015249(579-584)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015249
Mneimneh MSakallah KMoondanos J(2004)Preserving synchronizing sequences of sequential circuits after retimingASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)10.1109/ASPDAC.2004.1337658(579-584)Online publication date: 2004
https://doi.org/10.1109/ASPDAC.2004.1337658
Huang SGoto S(2001)On speeding up extended finite state machines using catalyst circuitryProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370538(583-588)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370538
Shi-Yu Huang (2001)On speeding up extended finite state machines using catalyst circuitryProceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)10.1109/ASPDAC.2001.913371(583-588)Online publication date: 2001
https://doi.org/10.1109/ASPDAC.2001.913371
Bommu SO'Neill NCiesielski M(2000)Retiming-based factorization for sequential logic optimizationACM Transactions on Design Automation of Electronic Systems10.1145/348019.3480685:3(373-398)Online publication date: 1-Jul-2000
https://dl.acm.org/doi/10.1145/348019.348068
Yu-Chung Lin Chien-Sung Chang Wen-Ling Chen Tsai-Ming Hsieh (2000)An adaptive algorithm for computing the initial states of retimed circuitsIEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394)10.1109/APCCAS.2000.913558(548-551)Online publication date: 2000
https://doi.org/10.1109/APCCAS.2000.913558
Kalla PCiesielski M(1999)Performance driven resynthesis by exploiting retiming-induced state register equivalenceProceedings of the conference on Design, automation and test in Europe10.1145/307418.307579(125-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307579
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Optimum retiming of large sequential circuits

Efficient retiming of large circuits

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