Retiming [7],| 8] is an optimization technique for sequential circuits which consists in modifying the positions of latches relative to blocks of combinational logic in order to minimize the maximum propagation delay between latches or to meet a given delay requirement while minimizing the number of latches. If the initial state of the circuit is meaningful, one must compute an equivalent initial state for the retimed circuit after retiming. In this paper we present a simple linear time algorithm to compute a correct initial state for a retimed circuit that can be used whenever the initial state of the original circuit satisfies a simple condition. If this condition is not originally satisfied, we show how it can be automatically enforced by a logic synthesis tool with no need for user intervention.