Preserving synchronizing sequences of sequential circuits after retiming
Abstract
References
Recommendations
Optimum retiming of large sequential circuits
VLSID '95: Proceedings of the 8th International Conference on VLSI DesignWe present a new, fast algorithm for optimally retiming large sequential circuits under the unit delay model. Our method consists of two main steps: (1) computation of the optimum clock period and (2) computation of a feasible retiming For the optimum ...
Efficient retiming of large circuits
Retiming, introduced by Leiserson and Saxe, is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock ...
Basic circuits for multi-valued sequential logic
Multi-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
Sponsors
- IPSJ: Information Processing Society of Japan
- IEEE Circuits and Systems Society
- SIGDA: ACM Special Interest Group on Design Automation
- IEICE: Institute of Electronics, Information and Communication Engineers
Publisher
IEEE Press
Publication History
Check for updates
Qualifiers
- Article
Conference
- IPSJ
- SIGDA
- IEICE
Acceptance Rates
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 91Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Other Metrics
Citations
Cited By
View allView Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in