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View all- Huang CChen JWey C(2017)PACESIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256140336:1(134-145)Online publication date: 1-Jan-2017
Clock Period Minimization with Minimum Leakage Power
Article No.: 9, Pages 1 - 33
Abstract
In the design of nonzero clock skew circuits, an increase of the short-path delay may improve circuit speed or reduce leakage power. However, the impact of increasing the short-path delay on the trade-off between circuit speed and leakage power has not been well studied. An analysis of previous works shows that they can be classified into two independent groups. One group uses extra buffers to increase the short-path delay for achieving the lower bound of the clock period; however, this group has a large overhead of leakage power. The other group uses the combination of threshold voltage assignment and gate sizing (TVA/GS) to increase the short-path delay as possible for reducing leakage power; however, this group often does not work with the lower bound of the clock period. Accordingly, this article considers the simultaneous application of buffer insertion and TVA/GS during clock skew scheduling. Our objective is to minimize the leakage power for working with the lower bound of the clock period. To the best of our knowledge, our approach is the first leakage-power-aware clock skew scheduling that guarantees working with the lower bound of the clock period. Benchmark data consistently show that our approach achieves good results in terms of both the circuit speed and the leakage power.
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Index Terms
- Clock Period Minimization with Minimum Leakage Power
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November 2015
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Publication History
Published: 02 December 2015
Accepted: 01 May 2015
Revised: 01 April 2015
Received: 01 December 2014
Published in TODAES Volume 21, Issue 1
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View all- Huang CChen JWey C(2017)PACESIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256140336:1(134-145)Online publication date: 1-Jan-2017
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