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View all- Huang CChen JWey C(2017)PACESIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256140336:1(134-145)Online publication date: 1-Jan-2017
Clock Period Minimization with Minimum Leakage Power
Article No.: 9, Pages 1 - 33
Abstract
In the design of nonzero clock skew circuits, an increase of the short-path delay may improve circuit speed or reduce leakage power. However, the impact of increasing the short-path delay on the trade-off between circuit speed and leakage power has not been well studied. An analysis of previous works shows that they can be classified into two independent groups. One group uses extra buffers to increase the short-path delay for achieving the lower bound of the clock period; however, this group has a large overhead of leakage power. The other group uses the combination of threshold voltage assignment and gate sizing (TVA/GS) to increase the short-path delay as possible for reducing leakage power; however, this group often does not work with the lower bound of the clock period. Accordingly, this article considers the simultaneous application of buffer insertion and TVA/GS during clock skew scheduling. Our objective is to minimize the leakage power for working with the lower bound of the clock period. To the best of our knowledge, our approach is the first leakage-power-aware clock skew scheduling that guarantees working with the lower bound of the clock period. Benchmark data consistently show that our approach achieves good results in terms of both the circuit speed and the leakage power.
References
[1]
R. B. Deokar and S. S. Sapatnekar. 1994. A Graph-theoretic approach to clock skew optimization. In Proceedings of the IEEE International Symposium on Circuits and Systems, 407--410.
[2]
J. P. Fishburn. 1990. Clock skew optimization. IEEE Trans. Comput. 39, 7, 945--951.
[3]
S. H. Huang, G. Y. Ghuo, and W. L. Huang. 2011. Minimum inserted buffers for clock period minimization. J. Inf. Sci. Engin. 27, 5, 1513--1526.
[4]
S. H. Huang and Y. T. Nieh. 2006. Synthesis of nonzero clock skew circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25, 6, 961--976.
[5]
K. Jeong, A. B. Kahng, and H. Yao. 2009. Revisiting the linear programming framework for leakage power vs. performance optimization. In Proceedings of the IEEE International Symposium on Quality Electronic Design, 127--134.
[6]
A. B. Kahng, S. Kang, H. Lee, I. L. Markov, and P. Thapar. 2013. High-performance gate sizing with a signoff timer. In Proceedings of the IEEE International Conference on Computer Aided Design, 450--457.
[7]
N. Karmarkar. 1984. A new polynomial-time algorithm for linear programming. Combinatorica. 4, 4, 373--395.
[8]
M. Ketkar and S. S. Sapatnekar. 2002. Standby power optimization via transistor sizing and dual threshold voltage assignment. In Proceedings of the IEEE International Conference on Computer Aided Design, 375--378.
[9]
L. Li, J. Sun, Y. Lu, H. Zhou, and X. Zeng. 2011. Low power discrete voltage assignment under clock skew scheduling. In Proceedings of the IEEE Asia and South Pacific Design Automation Conference, 515--520.
[10]
C. H. Lin, S. M. Syu, and T. Y. Ho. 2014. NBTI tolerance and leakage reduction using gate sizing. ACM J. Emerg. Technol. Comput. Syst. 11, 1, Article 4.
[11]
Y. Liu and J. Hu. 2010. A new algorithm for simultaneous gate sizing and threshold voltage assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29, 2, 223--234.
[12]
N. Maheshwari and S. S. Sapatnekar. 1999. Timing Analysis and Optimization of Sequential Circuits. Kluwer Academic Publishers.
[13]
M. Ni and S. O. Memik. 2008. Leakage-power-aware clock skew scheduling: converting stolen time into leakage power reduction. In Proceedings of the IEEE Design Automation Conference, 610--613.
[14]
W. Ning. 1994. Strongly NP-hard discrete gate sizing problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13, 8, 1045--1051.
[15]
M. M. Ozdal, C. Amin, A. Ayupov, S. Burns, G. Wilke, and C. Zhuo. 2013. An improved benchmark suite for the ISPD-2013 discrete cell sizing contest. In Proceedings of the ACM International Symposium on Physical Design, 168--170.
[16]
M. C. Papaefthymiou. 1994. Understanding retiming through maximum average-delay cycles. Math. Syst. Theory 27, 1, 65--84.
[17]
M. Rahman and C. Sechen. 2012. Post-synthesis leakage power minimization. In Proceedings of the IEEE Design, Automation & Test in Europe Conference and Exhibition, 99--104.
[18]
S. Shah, A. Srivastava, D. Sharma, D. Sylvester, D. Blaauw, and V. Zolotov. 2005. Discrete Vt assignment and gate sizing using a selfsnapping continuous formulation. In Proceedings of the IEEE International Conference on Computer Aided Design, 704--711.
[19]
N. V. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli. 1993. Minimum padding to satisfy short path constraints. In Proceedings of the IEEE International Conference on Computer Aided Design, 156--161.
[20]
B. Taskin and I. V. Kourtev. 2006. Delay insertion method in clock skew scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25, 4, 651--663.
[21]
M. Tie, H. Dong, T. Wang, and X. Chen. 2010. Dual-Vth leakage reduction with fast clock skew scheduling enhancement. In Proceedings of the IEEE Design, Automation & Test in Europe Conference and Exhibition, 520--525.
[22]
W. P. Tu, S. H. Huang, and C. H. Cheng. 2013. Co-synthesis of data paths and clock control paths for minimum-period clock gating. In Proceedings of the IEEE Design, Automation & Test in Europe Conference and Exhibition, 1831--1836.
[23]
H. H. Yeh, S. H. Huang, and Y. T. Nieh. 2014. Leakage-power-aware clock period minimization. In Proceedings of the IEEE Design, Automation & Test in Europe Conference and Exhibition, 1--6.
Index Terms
- Clock Period Minimization with Minimum Leakage Power
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November 2015
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Publication History
Published: 02 December 2015
Accepted: 01 May 2015
Revised: 01 April 2015
Received: 01 December 2014
Published in TODAES Volume 21, Issue 1
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View all- Huang CChen JWey C(2017)PACESIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256140336:1(134-145)Online publication date: 1-Jan-2017
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