extended-abstract

Between all and nothing - versatile aborts in hardware transactional memory

Authors:

Stephan Diestelhorst,

Martin Nowack,

Michael Spear,

Christof FetzerAuthors Info & Claims

SPAA '13: Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures

Pages 108 - 110

https://doi.org/10.1145/2486159.2486165

Published: 23 July 2013 Publication History

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Abstract

Hardware Transactional Memory (HTM) implementations are becoming available in commercial, off-the-shelf components. While generally comparable, some implementations deviate from the strict all-or-nothing property of pure Transactional Memory. We analyse these deviations and find that with small modifications, they can be used to accelerate and simplify both transactional and non-transactional programming constructs. At the heart of our extensions we enable access to the transaction's full register state in the abort handler in an existing HTM without extending the architectural register state. Access to the full register state enables applications in both transactional and non-transactional parallel programming: hybrid transactional memory; transactional escape actions; transactional suspend/resume; and alert-on-update.

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Cited By

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Park SHughes CPrvulovic MEvripidou SStenström PO'Boyle M(2018)Transactional pre-abort handlers in hardware transactional memoryProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243186(1-11)Online publication date: 1-Nov-2018
https://dl.acm.org/doi/10.1145/3243176.3243186

Index Terms

Between all and nothing - versatile aborts in hardware transactional memory

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Information

Published In

SPAA '13: Proceedings of the twenty-fifth annual ACM symposium on Parallelism in algorithms and architectures

July 2013

348 pages

ISBN:9781450315722

DOI:10.1145/2486159

General Chair:
Guy Blelloch
Carnegie Mellon University, USA
,
Program Chair:
Berthold Vöcking
RWTH Aachen University, Germany

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 July 2013

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SPAA '13

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SPAA '13: 25th ACM Symposium on Parallelism in Algorithms and Architectures

July 23 - 25, 2013

Québec, Montréal, Canada

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SPAA '13 Paper Acceptance Rate 31 of 130 submissions, 24%;

Overall Acceptance Rate 447 of 1,461 submissions, 31%

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Park SHughes CPrvulovic MEvripidou SStenström PO'Boyle M(2018)Transactional pre-abort handlers in hardware transactional memoryProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243186(1-11)Online publication date: 1-Nov-2018
https://dl.acm.org/doi/10.1145/3243176.3243186

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Cited By

Index Terms

Recommendations

Transactional Read-Modify-Write Without Aborts

Store Atomicity for Transactional Memory

Unbounded page-based transactional memory