Transactional memory architecture and implementation for IBM System z
C Jacobi, T Slegel, D Greiner - 2012 45th Annual IEEE/ACM …, 2012 - ieeexplore.ieee.org
C Jacobi, T Slegel, D Greiner
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012•ieeexplore.ieee.orgWe present the introduction of transactional memory into the next generation IBM System z
CPU. We first describe the instruction-set architecture features, including requirements for
enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise
EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be
embedded into the existing cache design and multiprocessor shared-memory infrastructure.
We explain practical reasons behind our choices. The zEC12 system is available since …
CPU. We first describe the instruction-set architecture features, including requirements for
enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise
EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be
embedded into the existing cache design and multiprocessor shared-memory infrastructure.
We explain practical reasons behind our choices. The zEC12 system is available since …
We present the introduction of transactional memory into the next generation IBM System z CPU. We first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure. We explain practical reasons behind our choices. The zEC12 system is available since September 2012.
ieeexplore.ieee.org