Cited By
View all- Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
Transactional pre-abort handlers in hardware transactional memory
Article No.: 33, Pages 1 - 11
Abstract
Commercially available hardware transactional memory (HTM) implementations resolve a number of potentially problematic situations by aborting a transaction, rather than add the hardware complexity needed to handle each situation more gracefully.
In this paper we propose pre-abort handlers, a general-purpose mechanism that invokes a software handler instead of aborting the transaction. The handler is executed non-transactionally while a transaction's execution is paused, allowing the handler to decide on and then perform the actions appropriate for the specific situation that caused the handler to be invoked.
We use our pre-abort handler mechanism to salvage a transaction's already-performed work in several common scenarios, and also to allow controlled nesting of non-transactional work within a transaction, without further changes to the hardware (beyond pre-abort handler support itself). In contrast, prior work on abort mitigation and on allowing non-transactional work within transactions requires dedicated hardware support for mitigation of each type of problematic situation.
References
[1]
L. Baugh and C. Zilles. 2008. An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory. In Performance Analysis of Systems and software, 2008. ISPASS 2008. IEEE International Symposium on. 54--62.
[2]
G. Blake, R.G. Dreslinski, and T. Mudge. 2011. Bloom Filter Guided Transaction Scheduling. In Intl. Symp. on High Performance Computer Architecture (HPCA '11). 75--86.
[3]
Geoffrey Blake, Ronald G. Dreslinski, and Trevor Mudge. 2009. Proactive Transaction Scheduling for Contention Management. In IEEE/ACM Intl. Symp. on Microarchitecture (MICRO 42). 156--167.
[4]
Colin Blundell, Joe Devietti, E. Christopher Lewis, and Milo M. K. Martin. 2007. Making the Fast Case Common and the Uncommon Case Simple in Unbounded Transactional Memory. In Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA '07). ACM, New York, NY, USA, 24--34.
[5]
Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, and David A. Wood. 2008. TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. In Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA '08). IEEE Computer Society, Washington, DC, USA, 127--138.
[6]
Harold W. Cain, Maged M. Michael, Brad Frey, Cathy May, Derek Williams, and Hung Le. 2013. Robust Architectural Support for Transactional Memory in the Power Architecture. In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13). ACM, New York, NY, USA, 225--236.
[7]
I. Calciu, J. Gottschlich, T. Shpeisman, M. Herlihy, and G. Pokam. 2014. Invyswell: A hybrid transactional memory for Haswell's restricted transactional memory. In 2014 23rd International Conference on Parallel Architecture and Compilation Techniques (PACT). 187--199.
[8]
J. Chung, D. R. Chakrabarti, and C. Cao Minh. 2010. Analysis on semantic transactional memory footprint for hardware transactional memory. In Workload Characterization (IISWC), 2010 IEEE International Symposium on. 1--11.
[9]
J. Chung, L. Yen, S. Diestelhorst, M. Pohlack, M. Hohmuth, D. Christie, and D. Grossman. 2010. ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory. In 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture. 39--50.
[10]
Peter Damron, Alexandra Fedorova, Yossi Lev, Victor Luchangco, Mark Moir, and Daniel Nussbaum. 2006. Hybrid Transactional Memory. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XII). ACM, New York, NY, USA, 336--346.
[11]
Dave Dice, Timothy L. Harris, Alex Kogan, Yossi Lev, and Mark Moir. 2014. Pitfalls of Lazy Subscription. In Workshop on the Theory of Transactional Memory (WTTM '14).
[12]
Stephan Diestelhorst, Martin Nowack, Michael Spear, and Christof Fetzer. 2013. Brief Announcement: Between All and Nothing - Versatile Aborts in Hardware Transactional Memory. In Proceedings of the Twenty-fifth Annual ACM Symposium on Parallelism in Algorithms and Architectures (SPAA '13). ACM, New York, NY, USA, 108--110.
[13]
Aleksandar Dragojević, Rachid Guerraoui, Anmol V. Singh, and Vasu Singh. 2009. Preventing Versus Curing: Avoiding Conflicts in Transactional Memories. In ACM Symp. on Principles of Distributed Computing (PODC '09). 7--16.
[14]
Lance Hammond, Vicky Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, and Kunle Olukotun. 2004. Transactional Memory Coherence and Consistency. In Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA '04). IEEE Computer Society, Washington, DC, USA, 102--. http://dl.acm.org/citation.cfm?id=998680.1006711
[15]
Tim Harris, James Larus, and Ravi Rajwar. 2010. Transactional memory. Synthesis Lectures on Computer Architecture 5, 1 (2010), 1--263.
[16]
Maurice Herlihy, Victor Luchangco, Mark Moir, and William N. Scherer, III. 2003. Software Transactional Memory for Dynamic-sized Data Structures. In Proceedings of the Twenty-second Annual Symposium on Principles of Distributed Computing (PODC '03). ACM, New York, NY, USA, 92--101.
[17]
Intel Corporation. 2012. Intel® Architecture Instruction Set Extensions Programming Reference.
[18]
C. Jacobi, T. Slegel, and D. Greiner. 2012. Transactional Memory Architecture and Implementation for IBM System Z. In Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on. 25--36.
[19]
Sanjeev Kumar, Michael Chu, Christopher J. Hughes, Partha Kundu, and Anthony Nguyen. 2006. Hybrid Transactional Memory. In Proceedings of the Eleventh ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP '06). ACM, New York, NY, USA, 209--220.
[20]
M. Lupon, G. Magklis, and A. Gonzalez. 2009. FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery. In Parallel Architectures and Compilation Techniques, 2009. PACT '09. 18th International Conference on. 293--302.
[21]
W. Maldonado, P. Marlier, P. Felber, J. Lawall, G. Muller, and E. Rivière. 2011. Deadline-aware scheduling for Software Transactional Memory. In Dependable Systems Networks (DSN), 2011 IEEE/IFIP 41st International Conference on. 257--268.
[22]
Austen McDonald, JaeWoong Chung, Brian D. Carlstrom, Chi Cao Minh, Hassan Chafı, Christos Kozyrakis, and Kunle Olukotun. 2006. Architectural Semantics for Practical Transactional Memory. In Proceedings of the 33rd Annual International Symposium on Computer Architecture (ISCA '06). IEEE Computer Society, Washington, DC, USA, 53--65.
[23]
Chi Cao Minh, Jaewoong Chung, Christos Kozyrakis, and Kunle Olukotun. 2008. STAMP: Stanford Transactional Applications for MultiProcessing. In IEEE International Symposium on Workload Characterization. 35--46.
[24]
N. Nethercote, R. Walsh, and J. Fitzhardinge. 2006. "Building Workload Characterization Tools with Valgrind". In 2006 IEEE International Symposium on Workload Characterization. 2--2.
[25]
James Poe, Chang-Burm Cho, and Tao Li. 2008. Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design. Computer Architecture and High Performance Computing, Symposium on 0 (2008), 159--166.
[26]
Jose Renau, Basilio Fraguela, James Tuck, Wei Liu, Milos Prvulovic, Luis Ceze, Smruti Sarangi, Paul Sack, Karin Strauss, and Pablo Montesinos. 2005. SESC simulator. http://sesc.sourceforge.net.
[27]
Michael F. Spear, Arrvindh Shriraman, Luke Dalessandro, Sandhya Dwarkadas, and Michael L. Scott. 2007. Nonblocking Transactions Without Indirection Using Alert-on-update. In Proceedings of the Nineteenth Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA '07). ACM, New York, NY, USA, 210--220.
[28]
Haris Volos, Andres Jaan Tack, Neelam Goyal, Michael M. Swift, and Adam Welc. 2009. xCalls: Safe I/O in Memory Transactions. In Proceedings of the 4th ACM European Conference on Computer Systems (EuroSys '09). ACM, New York, NY, USA, 247--260.
[29]
Adam Welc, Bratin Saha, and Ali-Reza Adl-Tabatabai. 2008. Irrevocable Transactions and Their Applications. In Proceedings of the Twentieth Annual Symposium on Parallelism in Algorithms and Architectures (SPAA '08). ACM, New York, NY, USA, 285--296.
[30]
Michael Wong and Victor Luchangco. 2014. SG5 Transactional Memory Support for C++ Update. http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2014/n4180.pdf.
[31]
Richard M. Yoo, Christopher J. Hughes, Konrad Lai, and Ravi Rajwar. 2013. Performance Evaluation of Intel® Transactional Synchronization Extensions for High-performance Computing. In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis (SC '13). ACM, New York, NY, USA, Article 19,11 pages.
[32]
Craig Zilles and Ravi Rajwar. 2007. Transactional Memory and the Birthday Paradox. In Proceedings of the Nineteenth Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA '07). ACM, New York, NY, USA, 303--304.
[33]
Ferad Zyulkyarov, Tim Harris, Osman S. Unsal, Adrían Cristal, and Mateo Valero. 2010. Debugging Programs That Use Atomic Blocks and Transactional Memory. In Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP '10). ACM, New York, NY, USA, 57--66.
Index Terms
- Transactional pre-abort handlers in hardware transactional memory
Recommendations
Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS ConferenceExploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...
Hybrid transactional memory
Proceedings of the 2006 ASPLOS ConferenceTransactional memory (TM) promises to substantially reduce the difficulty of writing correct, efficient, and scalable concurrent programs. But "bounded" and "best-effort" hardware TM proposals impose unreasonable constraints on programmers, while more ...
Hybrid transactional memory
PPoPP '06: Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programmingHigh performance parallel programs are currently difficult to write and debug. One major source of difficulty is protecting concurrent accesses to shared data with an appropriate synchronization mechanism. Locks are the most common mechanism but they ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
November 2018
494 pages
ISBN:9781450359863
DOI:10.1145/3243176
- General Chair:
- Skevos Evripidou,
- Program Chairs:
- Per Stenström,
- Michael O'Boyle
Copyright © 2018 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Sponsors
In-Cooperation
- IFIP WG 10.3: IFIP WG 10.3
- IEEE CS
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 01 November 2018
Check for updates
Author Tags
Qualifiers
- Research-article
Funding Sources
Conference
PACT '18
Sponsor:
PACT '18: International conference on Parallel Architectures and Compilation Techniques
November 1 - 4, 2018
Limassol, Cyprus
Acceptance Rates
Overall Acceptance Rate 121 of 471 submissions, 26%
Upcoming Conference
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 294Total Downloads
- Downloads (Last 12 months)57
- Downloads (Last 6 weeks)13
Reflects downloads up to 21 Sep 2024
Other Metrics
Citations
Cited By
View all- Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in