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Optimistic coalescing for heterogeneous register architectures

Authors:

Yunheung PaekAuthors Info & Claims

ACM SIGPLAN Notices, Volume 42, Issue 7

Pages 93 - 102

https://doi.org/10.1145/1273444.1254781

Published: 13 June 2007 Publication History

Abstract

In this paper, Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers which are all gathered in the same register file. Although this register architecture is still common in most general-purpose processors, embedded processors often contain heterogeneous registers which are scattered in physically different register files dedicated for each dissimilar purpose and use. In this work, we developed a modified algorithm for optimal coalescing that helps a register allocator for an embedded processor to better handle such heterogeneity of the register architecture. In the experiment, an existing register allocator was able to achieve up to 10% reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme.

References

[1]

Gregory J. Chaitin, Register allocation and spilling via graph coloring, SIGPLAN Symposium on Compiler Construction, 1982

Digital Library

[2]

V. Zivojnovic, et al., DSP processor/compiler co-design: a quantitative approach, 9th International Symposium on System Synthesis p. 108

Digital Library

[3]

Jinpyo Park, Soo-Mook Moon, Optimistic Register Coalescing, in the Proceedings of Parallel Architectures and Compilation Techniques (PACT) 98, 1998

Digital Library

[4]

T. Kong et. al, Precise register allocation for irregular architectures. In Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture (MICRO), page 297--307. IEEE computer Society Press, 1998.

Digital Library

[5]

B.Scholz et. al., Register allocation for irregular architectures. In Proceedings of the joint conference on Languages, Compilers and Tools for Embedded Systems (LCTES), pages 139--148. ACM Press, 2002.

Digital Library

[6]

D. Koes et. al., A Progressive Register Allocator for Irregular Architectures. In proceedings of the international Symposium on Code Generation and Optimization (CGO), 2005.

Digital Library

[7]

Michael D. Smith, et. al., A Generalized Algorithm for Graph-coloring register allocation, in the Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation (PLDI) 04, Vol39, Issue 6, 2004

Digital Library

[8]

Lal George, et. al., Iterated Register Coalescing, ACM Transactions on Programming Languages and Systems, Vol. 18, N0. 3, May 1996, Pages 300--324

Digital Library

[9]

Minwook Ahn, et. al., A Code Generation Approach for Heterogeneous Register Architectures, in the Proceedings of the 11th Annual Workshop on the Interaction between Compilers and Computer Architecture, 2007

[10]

C. Liem, T. et. al., Register Assignment through Resource Classification for ASIP Microcode Generation, in the Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, 1994

Digital Library

[11]

P. Paulin, et. al., DSP Design Tool Requirements for Embedded Systems: A Telecommunications Industrial Perspective, in Journal of VLSI Signal Processing, 1994

Digital Library

[12]

H. Feuerhahn, Data Flow Driven Resource Allocation in a Retargetable Microde Compiler, International Symposium on Microarchitecture, 1988, pp. 105--107

Digital Library

[13]

R. Stallman, Using and Porting GNU CC, Free Software Foundation, June 1993

[14]

Guido Araujo, et. al., Code Generation for Fixed-Point DSPs, ACM Transactions on Design Automation of Electronic Systems(TODAES), Vol 3, Issue 2, 1998

Digital Library

[15]

V. Zivojnovic, et. al., DSPstone: A DSP-Oriented Benchmarking Methodology, in the Proceedings of International Conference on Signal Processing Applications and Technology (ICSPAT)'94 -- Dallas, Oct. 1994.

[16]

Chunho Lee, et. al., MediaBench: a tool for evaluating and synthesizing multimedia andcommunications systems, in the Proceedings of 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 1997.

Digital Library

[17]

Jenq-Kuen Lee, et. al., Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files, in the Proceedings of the 19th International Workshop on Languages and Compilers for Parallel Computing (LCPC) 2006

[18]

Jean-Marc Daveau, et. al., A retargetable register allocation framework for embedded processors, in the Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2004

Digital Library

[19]

P. Briggs. Register Allocation via Graph Coloring, Ph.d Thesis, Rice University, April 1992

Digital Library

Cited By

Wu CLu CLee J(2014)Register spilling via transformed interference equations for PAC DSP architectureConcurrency and Computation: Practice & Experience10.1002/cpe.305126:3(779-799)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1002/cpe.3051
Pereira FPalsberg J(2010)Punctual coalescingProceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction10.1007/978-3-642-11970-5_10(165-184)Online publication date: 20-Mar-2010
https://dl.acm.org/doi/10.1007/978-3-642-11970-5_10
Carroll DMeyerson ATagiku B(2009)Approximations for Aligned Coloring and Spillage Minimization in Interval and Chordal GraphsProceedings of the 12th International Workshop and 13th International Workshop on Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques10.1007/978-3-642-03685-9_3(29-41)Online publication date: 21-Aug-2009
https://dl.acm.org/doi/10.1007/978-3-642-03685-9_3
Show More Cited By

Index Terms

Optimistic coalescing for heterogeneous register architectures
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

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LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

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Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 42, Issue 7

Proceedings of the 2007 LCTES conference

July 2007

241 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/1273444

Issue’s Table of Contents

LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
June 2007
258 pages
ISBN:9781595936325
DOI:10.1145/1254766
General Chair:
Santosh Pande
Georgia Institute of Technology, USA
,
Program Chair:
Zhiyuan Li
Purdue University, USA

Copyright © 2007 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2007

Published in SIGPLAN Volume 42, Issue 7

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Cited By

Wu CLu CLee J(2014)Register spilling via transformed interference equations for PAC DSP architectureConcurrency and Computation: Practice & Experience10.1002/cpe.305126:3(779-799)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1002/cpe.3051
Pereira FPalsberg J(2010)Punctual coalescingProceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction10.1007/978-3-642-11970-5_10(165-184)Online publication date: 20-Mar-2010
https://dl.acm.org/doi/10.1007/978-3-642-11970-5_10
Carroll DMeyerson ATagiku B(2009)Approximations for Aligned Coloring and Spillage Minimization in Interval and Chordal GraphsProceedings of the 12th International Workshop and 13th International Workshop on Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques10.1007/978-3-642-03685-9_3(29-41)Online publication date: 21-Aug-2009
https://dl.acm.org/doi/10.1007/978-3-642-03685-9_3
Ahn MPaek Y(2009)Fast Code Generation for Embedded Processors with Aliased Heterogeneous RegistersTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_9(149-172)Online publication date: 22-Apr-2009
https://dl.acm.org/doi/10.1007/978-3-642-00904-4_9
Ahn MPaek Y(2009)Fast Code Generation for Embedded Processors with Aliased Heterogeneous RegistersTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_9(149-172)Online publication date: 22-Apr-2009
https://dl.acm.org/doi/10.1007/978-3-642-00904-4_9

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