Cited By
View all- Yu QAmpadu PYu QAmpadu P(2011)A Flexible Parallel Simulator for Networks-on-Chip with Error ControlTransient and Permanent Error Control for Networks-on-Chip10.1007/978-1-4614-0962-5_6(117-149)Online publication date: 27-Sep-2011
A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations
Pages 263 - 264
Abstract
Error control is imperative for reliable Networks-on-Chip (NoCs) design. In this demo session, we will present a CAD tool---a flexible and parallel NoC simulator. Our simulator evaluates the impact of different error control mechanisms on NoC performance and energy consumption in various noise and traffic injection scenarios. Our message passing interface language-based simulator can be executed on multiprocessors or server clusters. Multiple built-in blocks provide flexibility to evaluate different error control methods.
References
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Q. Yu and P. Ampadu, "A flexible parallel simulator for networks-on-chip with error control," IEEE Trans. on Computer-Aided Design of Integr. Circuits and Syst. (TCAD), vol. 29, no. 1, pp. 103--116, Jan. 2010.
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Index Terms
- A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations
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Published In
May 2011
282 pages
ISBN:9781450307208
DOI:10.1145/1999946
- General Chairs:
- Radu Marculescu,
- Mike Kishinevsky,
- Program Chairs:
- Ran Ginosar,
- Karam S. Chatha
Copyright © 2011 Authors.
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Association for Computing Machinery
New York, NY, United States
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Published: 01 May 2011
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View all- Yu QAmpadu PYu QAmpadu P(2011)A Flexible Parallel Simulator for Networks-on-Chip with Error ControlTransient and Permanent Error Control for Networks-on-Chip10.1007/978-1-4614-0962-5_6(117-149)Online publication date: 27-Sep-2011
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