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Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained acceleration previously impeded by communication overhead to a ...

PARSEC is a massively parallel Density-Functional-Theory (DFT) code. Within the modernization effort towards the new Intel Knights Landing platform, we adapted the main computational kernel, represented as high-order finite-difference stencils, to use ...

Driven by the utilization wall and the Dark Silicon effect, energy efficiency has become a key research area in microprocessor design. Vectorization, parallelization, specialization and heterogeneity are the key design points to deal with the utilization ...

Recent technology trends have indicated that, although device sizes will continue to scale as they have in the past, supply voltage scaling has ended. As a result, future chips can no longer rely on simply increasing the operational core count to ...

Off-Chip miss latency remains a bottleneck even in the modern chip multiprocessors. Recent research advocates memory streaming techniques to alleviate the performance bottleneck caused by the high latencies of off-chip memory accesses. Memory streaming ...

Error control is imperative for reliable Networks-on-Chip (NoCs) design. In this demo session, we will present a CAD tool---a flexible and parallel NoC simulator. Our simulator evaluates the impact of different error control mechanisms on NoC ...

Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TLB designs to lower access times and miss rates; these, however, have been ...

In this study, a reliability analysis was performed for the aerodynamic analysis. Among various reliability analysis methods, the moment method was used and the results were compared with other methods. The reliability of aerodynamic analysis of a 2D ...

In this paper we investigate the performance of routing strategies in ad hoc networks. An ad hoc network operates without a central entity or infrastructure, and is composed of highly mobile network hosts. In this environment, routes tend to be multihop ...

When used to simulate manufacturing systems, most existing parallel simulation languages cannot easily implement some features of those systems, such as the scheduling rules of a machine or the sharing of operators by multiple machines. This paper ...

Simulation is the main tool for studying networking protocols before deploying them in a wide scale, or for understanding how they are expected to behave under various conditions. IRLSim is a new packet level network simulator that we developed in the ...