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Microarchitectural synthesis of VLSI designs with high test concurrency

Published: 06 June 1994 Publication History
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References

[1]
M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[2]
P. H. Bardell, W. H. McAnney, and 3. Savir. Built-In Test for VLSL Wiley-Interscience, 1987.
[3]
C.-H. Chen, C. Wu, and D. G. Saab. BETA: Behavioral Testability Analysis. Proceedings of the IEEE Conference on Computer Aided Design, pages 202-205, November 1991.
[4]
S. Chiu and C. A. Papachristou. A Design for Testability Scheme with Applications to Data Path Synthesis. Proceedings of the 28th Design Automation Conference, A CM-IEEE, pages 271-277, June 1991.
[5]
I. G. Harris and A. Orailo~lu. Effective Test Path Definition Assisted by High-Level Synthesis Modifications. Proceedings of the Synthesis and Simulation Meeting and International Exchange (SASIMI), pages 187-195, October 1993. Nara, Japan.
[6]
I. G. Harris and A. Orailo~lu. Fine-Grained Concurrency in Test Scheduling for PartiM-Intrusion BIST. Proceedings of the European Design Automation Conference, pages 119-123, February 1994.
[7]
R. Karri and A. Orailo~lu. Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. In Proceedings of the 22nd International Symposium on Fault-Tolerant Computing, pages 519-526, July 1992.
[8]
R. Karri and A. Orailo~lu. Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis. In Proceedings of the 31st Design Automation Conference, June 1994.
[9]
S. Y. Kung, H. J. Whitehouse, and T. Kailath. VLSI and Modern Signal Processing. Prentice-HM1, 1985.
[10]
T.-C. Lee, W. H. Wolf, N. K. Jha, and J. M. Acken. Behavioral Synthesis for Easy Testability in Data Path Allocation. Proceedings of the IEEE Conference on Computer Design, pages 29-32, October 1992.
[11]
E. J. McCluskey. Built-In Self-Test Techniques. IEEE Design and Test, pages 21-28, April 1985.
[12]
Mujumdar, K. Saluja, and R Jain. Incorporating Testability Considerations in High-Level Synthesis. 22nd Fault Tolerant Computing Symposium, pages 272-279, July 1992.
[13]
A. Orailo~lu and I. G. Harris. Test Path Generation and Test Scheduling for Self-Testable Designs. Proceedings of the IEEE Conference on Computer Design, pages 528- 531, October 1993.
[14]
N. Park and A. C. Parker. Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications. IEEE Transactions on Computer Aided Design, 7(3):356- 370, March 1988.
[15]
P. G. Paulin and 3. P. Knight. Force-Directed Scheduling for the Behavioral Synthesis of ASIC's. IEEE Transactions on Computer Aided Design, 8(6):661-679, June 1989.

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  • (2014)High-Level Test SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/262775419:4(1-27)Online publication date: 29-Aug-2014
  • (2006)BIST hardware synthesis for RTL data paths based on test compatibility classesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.89286119:11(1375-1385)Online publication date: 1-Nov-2006
  • (2006)A controller redesign technique to enhance testability of controller-data path circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.68126517:2(157-168)Online publication date: 1-Nov-2006
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        cover image ACM Conferences
        DAC '94: Proceedings of the 31st annual Design Automation Conference
        June 1994
        739 pages
        ISBN:0897916530
        DOI:10.1145/196244
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 06 June 1994

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        Cited By

        View all
        • (2014)High-Level Test SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/262775419:4(1-27)Online publication date: 29-Aug-2014
        • (2006)BIST hardware synthesis for RTL data paths based on test compatibility classesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.89286119:11(1375-1385)Online publication date: 1-Nov-2006
        • (2006)A controller redesign technique to enhance testability of controller-data path circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.68126517:2(157-168)Online publication date: 1-Nov-2006
        • (2006)Nonscan design-for-testability techniques using RT-level design informationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66423016:12(1488-1506)Online publication date: 1-Nov-2006
        • (2001)An integrated high-level test synthesis algorithm for built-in self-testable designsSymposium on Integrated Circuits and Systems Design10.1109/SBCCI.2001.953013(115-121)Online publication date: 2001
        • (2001)High-level data path synthesis for built-in self-test designs2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233)10.1109/PACRIM.2001.953577(279-282)Online publication date: 2001
        • (2001)Built-in self-testable data path synthesisProceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems10.1109/IWV.2001.923143(78-84)Online publication date: 2001
        • (2001)An improved high-level built-in self-test synthesis algorithmICECS 2001 8th IEEE International Conference on Electronics Circuits and Systems (Cat No 01EX483) ICECS-0110.1109/ICECS.2001.957802(549-552 vol.1)Online publication date: 2001
        • (2001)A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST SynthesisJournal of Electronic Testing: Theory and Applications10.1023/A:101222771532717:3-4(331-339)Online publication date: 1-Jun-2001
        • (2000)BISTing Data Paths at Behavioral LevelProceedings of the 2000 IEEE International Test Conference10.5555/839295.843665Online publication date: 3-Oct-2000
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