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Microarchitectural synthesis of VLSI designs with high test concurrency

Authors:

Ian G. Harris,

Alex OrailogluAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 206 - 211

https://doi.org/10.1145/196244.196353

Published: 06 June 1994 Publication History

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Cited By

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Ravi SJoseph M(2014)High-Level Test SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/262775419:4(1-27)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2627754
Nicolici NAl-Hashimi BBrown AWilliams A(2006)BIST hardware synthesis for RTL data paths based on test compatibility classesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.89286119:11(1375-1385)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.892861
Dey SGangaram VPotkonjak M(2006)A controller redesign technique to enhance testability of controller-data path circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.68126517:2(157-168)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.681265
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Index Terms

Microarchitectural synthesis of VLSI designs with high test concurrency
1. Hardware

Recommendations

High-level synthesis of VLSI designs for scientific programs
Microarchitectural synthesis for rapid BIST testing

The impact of testability on design cost necessitates its consideration during the earliest stages of synthesis. Built-in self test (BIST) is an accepted testing approach, but its application to many designs is limited by the long test application time ...
High level VLSI synthesis for multichip designs

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Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 06 June 1994

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DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Ravi SJoseph M(2014)High-Level Test SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/262775419:4(1-27)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2627754
Nicolici NAl-Hashimi BBrown AWilliams A(2006)BIST hardware synthesis for RTL data paths based on test compatibility classesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.89286119:11(1375-1385)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.892861
Dey SGangaram VPotkonjak M(2006)A controller redesign technique to enhance testability of controller-data path circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.68126517:2(157-168)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.681265
Dey SPotkonjak M(2006)Nonscan design-for-testability techniques using RT-level design informationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66423016:12(1488-1506)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.664230
Yang LMuzio J(2001)An integrated high-level test synthesis algorithm for built-in self-testable designsSymposium on Integrated Circuits and Systems Design10.1109/SBCCI.2001.953013(115-121)Online publication date: 2001
https://doi.org/10.1109/SBCCI.2001.953013
Laurence Tainruo Yang Muzio J(2001)High-level data path synthesis for built-in self-test designs2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233)10.1109/PACRIM.2001.953577(279-282)Online publication date: 2001
https://doi.org/10.1109/PACRIM.2001.953577
Yang LMuzio J(2001)Built-in self-testable data path synthesisProceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems10.1109/IWV.2001.923143(78-84)Online publication date: 2001
https://doi.org/10.1109/IWV.2001.923143
(2001)An improved high-level built-in self-test synthesis algorithmICECS 2001 8th IEEE International Conference on Electronics Circuits and Systems (Cat No 01EX483) ICECS-0110.1109/ICECS.2001.957802(549-552 vol.1)Online publication date: 2001
https://doi.org/10.1109/ICECS.2001.957802
Berthelot DFlottes MRouzeyre B(2001)A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST SynthesisJournal of Electronic Testing: Theory and Applications10.1023/A:101222771532717:3-4(331-339)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.1023/A%3A1012227715327
Berthelot DFlottes MRouzeyre B(2000)BISTing Data Paths at Behavioral LevelProceedings of the 2000 IEEE International Test Conference10.5555/839295.843665Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843665
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Index Terms

Recommendations

High-level synthesis of VLSI designs for scientific programs

Microarchitectural synthesis for rapid BIST testing

High level VLSI synthesis for multichip designs