article

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

Authors:

B. RouzeyreAuthors Info & Claims

Journal of Electronic Testing: Theory and Applications, Volume 17, Issue 3-4

Pages 331 - 339

https://doi.org/10.1023/A:1012227715327

Published: 01 June 2001 Publication History

Abstract

This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution.

References

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Digital Library

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Cited By

Wang JCardoso PGonzalez JStrum MPires R(2004)Datapath BIST Insertion Using Pre-Characterized Area and Testability DataJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000039602.34708.b220:4(333-344)Online publication date: 1-Aug-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000039602.34708.b2

Index Terms

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
1. Hardware
  1. Hardware test
  2. Robustness

Index terms have been assigned to the content through auto-classification.

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Copyright © Copyright © 2001 Kluwer Academic Publishers.

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Kluwer Academic Publishers

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Published: 01 June 2001

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Cited By

Wang JCardoso PGonzalez JStrum MPires R(2004)Datapath BIST Insertion Using Pre-Characterized Area and Testability DataJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000039602.34708.b220:4(333-344)Online publication date: 1-Aug-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000039602.34708.b2

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