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Estimation of average switching activity in combinational logic circuits using symbolic simulation

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 16, Issue 1

Pages 121 - 127

https://doi.org/10.1109/43.559336

Published: 01 November 2006 Publication History

Abstract

We address the problem of estimating the average switching activity of combinational circuits under random input sequences. Switching activity is strongly affected by gate delays, and for this reason we use a variable delay model in estimating switching activity. Unlike most probabilistic methods that estimate switching activity, our method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals. This method assumes a particular delay model and further assumes that the primary inputs to the combinational circuit are uncorrelated. Both these assumptions can be relaxed at the cost of increased complexity. We describe extensions to handle transmission gates and inertial delays in this paper

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Lyu ZShen J(2024)An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuitsMicroelectronics Journal10.1016/j.mejo.2024.106143146:COnline publication date: 1-Apr-2024
https://dl.acm.org/doi/10.1016/j.mejo.2024.106143
Strauch T(2023)MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven PrototypingProceedings of the 34th International Workshop on Rapid System Prototyping10.1145/3625223.3649276(1-7)Online publication date: 21-Sep-2023
https://dl.acm.org/doi/10.1145/3625223.3649276
Deligiannis NFaller TCantoro RPaxian TBecker BReorda M(2023)Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSATIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325246742:11(4270-4281)Online publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3252467
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 16, Issue 1

November 2006

127 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Lyu ZShen J(2024)An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuitsMicroelectronics Journal10.1016/j.mejo.2024.106143146:COnline publication date: 1-Apr-2024
https://dl.acm.org/doi/10.1016/j.mejo.2024.106143
Strauch T(2023)MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven PrototypingProceedings of the 34th International Workshop on Rapid System Prototyping10.1145/3625223.3649276(1-7)Online publication date: 21-Sep-2023
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Deligiannis NFaller TCantoro RPaxian TBecker BReorda M(2023)Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSATIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325246742:11(4270-4281)Online publication date: 1-Nov-2023
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Xiao WQian WMitra TYoung EXiong J(2022)ASPPLNProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549456(1-9)Online publication date: 30-Oct-2022
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Durrani YRiesgo T(2014)Power estimation for intellectual property-based digital systems at the architectural levelJournal of King Saud University - Computer and Information Sciences10.1016/j.jksuci.2014.03.00526:3(287-295)Online publication date: 1-Sep-2014
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Sampaio CMonteiro JSilveira L(2012)Analysis of the conditions for the worst case switching activity in integrated circuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-011-9782-770:2(229-240)Online publication date: 1-Feb-2012
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Liu YZhang TParhi K(2010)Computation error analysis in digital signal processing systems with overscaled supply voltageIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201286318:4(517-526)Online publication date: 1-Apr-2010
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Alioto MConsoli EPalumbo G(2010)Flip-flop energy/performance versus clock slope and impact on the clock network designIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.203011357:6(1273-1286)Online publication date: 1-Jun-2010
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Czajkowski TBrown S(2010)Decomposition-based vectorless toggle rate computation for FPGA circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206125029:11(1723-1735)Online publication date: 1-Nov-2010
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Design of Memristor-Based Combinational Logic Circuits

Reliability evaluation of combinational logic circuits by symbolic simulation

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