Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1109/ICIMT.2009.42guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
Article

Quaternary CMOS Combinational Logic Circuits

Published: 16 December 2009 Publication History

Abstract

Good Characteristics and advantages of multi-valued logic (MVL) electronic systems and circuits are created great interest for its practical implementation. This paper presents voltage mode quaternary CMOS circuit design using 90nm technology. Basic gates such as quaternary inverter, NMAX, NMIN and Quaternary multiplexer are designed and simulated. Low power consumption of 14 µ W is observed at 2.2GHz with 1.2 V power supply. Circuits are verified using HSPICE simulations. The circuits described here are also suitable to be implemented in classical CMOS VLSI technology.
  1. Quaternary CMOS Combinational Logic Circuits

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image Guide Proceedings
    ICIMT '09: Proceedings of the 2009 International Conference on Information and Multimedia Technology
    December 2009
    523 pages
    ISBN:9780769539225

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 16 December 2009

    Author Tags

    1. multi-valued logic
    2. nmin and nmax circuits
    3. quaternary logic

    Qualifiers

    • Article

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • 0
      Total Citations
    • 0
      Total Downloads
    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 22 Nov 2024

    Other Metrics

    Citations

    View Options

    View options

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media