research-article

EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions

Author:

T. SasaoAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 12, Issue 5

Pages 621 - 632

https://doi.org/10.1109/43.277608

Published: 01 November 2006 Publication History

Abstract

Minimization of AND-EXOR programmable logic arrays (PLAs) with input decoders corresponds to minimization of the number of products in Exclusive-OR sum-of-products expressions (ESOPs) for multiple-valued-input two-valued-output functions. A simplification algorithm for ESOPs that iteratively reduces the number of the products in ESOPs and then reduces the number of the literals is presented. Various rules are used to replace a pair of products with another one. Many AND-EXOR PLAs for arithmetic circuits have been simplified. In most cases, AND-EXOR PLAs required fewer products than AND-OR PLAs

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Das APradhan S(2016)Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic CircuitsVLSI Design10.1155/2016/31912862016Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1155/2016/3191286
Tara NBabu H(2016)Synthesis of reversible PLA using products sharingJournal of Computational Electronics10.1007/s10825-015-0762-515:2(420-428)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1007/s10825-015-0762-5
Abdessaied NSoeken MKirkedal Thomsen MDrechsler R(2014)Upper bounds for reversible circuits based on Young subgroupsInformation Processing Letters10.1016/j.ipl.2014.01.003114:6(282-286)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1016/j.ipl.2014.01.003
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 12, Issue 5

November 2006

184 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Das APradhan S(2016)Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic CircuitsVLSI Design10.1155/2016/31912862016Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1155/2016/3191286
Tara NBabu H(2016)Synthesis of reversible PLA using products sharingJournal of Computational Electronics10.1007/s10825-015-0762-515:2(420-428)Online publication date: 1-Jun-2016
https://dl.acm.org/doi/10.1007/s10825-015-0762-5
Abdessaied NSoeken MKirkedal Thomsen MDrechsler R(2014)Upper bounds for reversible circuits based on Young subgroupsInformation Processing Letters10.1016/j.ipl.2014.01.003114:6(282-286)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1016/j.ipl.2014.01.003
Bernasconi ACiriani VLuccio FPagli L(2013)Compact DSOP and Partial DSOP FormsTheory of Computing Systems10.1007/s00224-013-9447-253:4(583-608)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1007/s00224-013-9447-2
Mitra SJamal LKaneko MHasan Babu HBrunvard EStevens KCavallaro JZhang T(2012)An efficient approach for designing and minimizing reversible programmable logic arraysProceedings of the great lakes symposium on VLSI10.1145/2206781.2206834(215-220)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206834
Mizuki TTsubata HNishizeki T(2009)Minimizing AND-EXOR Expressions for Multiple-Valued Two-Input Logic FunctionsProceedings of the 6th Annual Conference on Theory and Applications of Models of Computation10.1007/978-3-642-02017-9_33(301-310)Online publication date: 12-May-2009
https://dl.acm.org/doi/10.1007/978-3-642-02017-9_33
Debnath DSasao T(2007)A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR NetworksIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e90-a.5.932E90-A:5(932-940)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1093/ietfec/e90-a.5.932
Bernasconi ACiriani VDrechsler RVilla TGielen G(2006)Efficient minimization of fully testable 2-SPP networksProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131839(1300-1305)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131839
Kalathas MVoudouris DPapakonstantinou GQu GIsmail YNarayanan VZhou H(2006)A heuristic algorithm to minimize ESOPs for multiple-output incompletely specified functionsProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127990(357-361)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127990
Mizuki TOtagiri TSone H(2006)Secure computations in a minimal model using multiple-valued ESOP expressionsProceedings of the Third international conference on Theory and Applications of Models of Computation10.1007/11750321_52(547-554)Online publication date: 15-May-2006
https://dl.acm.org/doi/10.1007/11750321_52
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