research-article

Formal verification of sequential hardware: a tutorial

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M. C. McFarlandAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 12, Issue 5

Pages 633 - 654

https://doi.org/10.1109/43.277609

Published: 01 November 2006 Publication History

Abstract

Various formal verification techniques and how they can be applied to sequential hardware, especially at the register-transfer level, are examined. The basic elements of a verification system, as illustrated on the relatively simple problem of verifying combinational circuits, are presented. The more complex problems involved in analyzing sequential systems and the techniques that have been developed to solve them are then considered. Throughout, the focus is on those techniques whose utility has been demonstrated on real systems, including higher order logic, temporal logic, predicate transformers, state-machine models, and model checkers

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Kaeslin H(2014)Top-Down Digital VLSI DesignundefinedOnline publication date: 18-Dec-2014
Weaver CAustin T(2001)A Fault Tolerant Approach to Microprocessor DesignProceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)10.5555/647882.738066(411-420)Online publication date: 1-Jul-2001
Kroening DPaul WRabaey J(2001)Automated pipeline designProceedings of the 38th annual Design Automation Conference10.1145/378239.379071(810-815)Online publication date: 22-Jun-2001
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Formal verification of sequential hardware: a tutorial

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 12, Issue 5

November 2006

184 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Kaeslin H(2014)Top-Down Digital VLSI DesignundefinedOnline publication date: 18-Dec-2014
Weaver CAustin T(2001)A Fault Tolerant Approach to Microprocessor DesignProceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)10.5555/647882.738066(411-420)Online publication date: 1-Jul-2001
Kroening DPaul WRabaey J(2001)Automated pipeline designProceedings of the 38th annual Design Automation Conference10.1145/378239.379071(810-815)Online publication date: 22-Jun-2001
Seshadri SAbraham J(2001)Frequency Response Verification of Analog Circuits Using Global Optimization TechniquesJournal of Electronic Testing: Theory and Applications10.1023/A:101275111874617:5(395-408)Online publication date: 1-Oct-2001
Utamaphethai NBlanton RShen J(2000)Effectiveness of Microarchitecture Test Program GenerationIEEE Design & Test10.1109/54.89500517:4(38-49)Online publication date: 1-Oct-2000
Utamaphethai NBlanton RShen J(2000)A Buffer-Oriented Methodology for Microarchitecture ValidationJournal of Electronic Testing: Theory and Applications10.1023/A:100838452195416:1-2(49-65)Online publication date: 1-Feb-2000
Huggins JCampenhout D(1998)Specification and verification of pipelining in the ARM2 RISC microprocessorACM Transactions on Design Automation of Electronic Systems10.1145/296333.2963453:4(563-580)Online publication date: 1-Oct-1998
Bartos TFristacky N(1996)Verifying Timing Consistency in Formal SpecificationsIEEE Design & Test10.1109/54.48577813:1(8-15)Online publication date: 1-Mar-1996
Hedrich LBarke ERudell R(1995)A formal approach to nonlinear analog circuit verificationProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.224870(123-127)Online publication date: 1-Dec-1995
Kuehlmann ASrinivasan ALaPotin D(1995)Verity—a formal verification program for custom CMOS circuitsIBM Journal of Research and Development10.1147/rd.391.014939:1-2(149-165)Online publication date: 1-Feb-1995
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