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Efficient minimization of fully testable 2-SPP networks

Published: 06 March 2006 Publication History

Abstract

The paper presents a heuristic algorithm for the minimization of 2-SPP networks, i.e., three-level EXOR-AND-OR forms with EXOR gates restricted to fan-in 2. Previous works had presented exact algorithms for the minimization of unrestricted SPP networks and of 2-SPP networks. The exact minimization procedures were formulated as covering problems as in the minimization of SOP forms and had worst-case exponential complexity. Extending the expand-irredundant-reduce paradigm of the ESPRESSO heuristic, we propose a minimization algorithm for 2-SPP networks that iterates local minimization and reshape of a solution until further improvement. We introduce also the notion of EXOR-irredundant to prove that OR-AND-EXOR irredundant networks are fully testable and guarantee that our algorithm yields OR-AND-EXOR irredundant solutions. We report a large set of experiments showing impressive high-quality results with affordable run times, handling also examples whose exact solutions could not be computed.

References

[1]
A. Bernasconi, V. Ciriani, R. Drechsler, and T. Villa. Efficient Minimization of Fully Testable 2-SPP Networks. Technical Report TR-05-23, University of Pisa, 2005.
[2]
R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.
[3]
M. Breuer and A. Friedman. Diagnosis & Reliable Design of Digital Systems. Computer Science Press, 1976.
[4]
V. Ciriani. Synthesis of SPP Three-Level Logic Networks using Affine Spaces. IEEE Transactions on TCAD, 22(10):1310--1323, 2003.
[5]
V. Ciriani and A. Bernasconi. 2-SPP: a Practical Trade-Off between SP and SPP Synthesis. In 5th International Workshop on Boolean Problems (IWSBP2002), pages 133--140, 2002.
[6]
V. Ciriani, A. Bernasconi, and R. Drechsler. Testability of SPP Three-Level Logic Networks. In IFIP 12-th International Conference on Very Large Scale Integration, (VLSI-SOC), pages 331--336, 2003.
[7]
G. Hachtel and F. Somenzi. Logic Synthesis and Verification Algorithms. Kluwer Academy Publishers, 1996.
[8]
T. Kozlowski, E. L. Dagless, and J. M. Saul. An Enhanced Algorithm for the Minimization of Exclusive-Or Sum-Of-Products for Incompletely Specified Functions. In The Proceedings of the International Conference on Computer Design, pages 244--249, 1995.
[9]
F. Luccio and L. Pagli. On a New Boolean Function with Applications. IEEE Transactions on Computers, 48(3):296--310, 1999.
[10]
S. Minato. Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems. In ACM/IEEE 30th Design Automation Conference (DAC), pages 272--277, 1993.
[11]
R. Rudell and A. Sangiovanni-Vincentelli. Multiple-valued minimization for PLA optimization. IEEE Transactions on Computer-Aided Design, CAD-6:727--750, Sept. 1987.
[12]
T. Sasao. EXMIN2: A Simplification Algorithm for Exclusive-OR-Sum-of Products Expressions for Multiple-Valued-Input Two-Valued-Output Functions. IEEE Transactions on Computer-Aided Design, 12:621--632, 1993.
[13]
E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Technical report, University of Berkeley, 1992.
[14]
S. Yang. Synthesis on Optimization Benchmarks. User guide, Microelectronic Center, 1991.

Cited By

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  • (2011)Universal logic modules based on double-gate carbon nanotube transistorsProceedings of the 48th Design Automation Conference10.1145/2024724.2024921(884-889)Online publication date: 5-Jun-2011
  • (2008)The optimization of kEP-SOPsACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/1344418.134443113:2(1-31)Online publication date: 23-Apr-2008

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Information

Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings
March 2006
1390 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2011)Universal logic modules based on double-gate carbon nanotube transistorsProceedings of the 48th Design Automation Conference10.1145/2024724.2024921(884-889)Online publication date: 5-Jun-2011
  • (2008)The optimization of kEP-SOPsACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/1344418.134443113:2(1-31)Online publication date: 23-Apr-2008

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