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Efficient FFT network testing and diagnosis schemes

Published: 01 June 2002 Publication History

Abstract

We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usualiy are required in order to guarantee high-quality products. We propose M-testability conditions for FFT butterfly, omega, and flip networks at the double-multiply-subtract-add (DMSA) module level. A novel design-for-testability technique based on the functional bijectivity property of the specified modules to detect faults other than the cell faults is presented. It guarantees 100% Combinational fault coverage with negligible hardware overhead--about 0.17% for an FFT network with 16-bit operand words, independent of the network size. Our design requires fewer test vectors compared with previous ones--a factor of up to 1/(6 × 25n), where n is the word length. We also propose C-diagnosability conditions and a C-diagnosable FFT network design. By properly exchanging and blocking certain fault propagation paths, a faulty DMSA module can be located using a two-phase deterministic algorithm. The blocking mechanism can be implemented with no additional hardware. Compared with previous schemes, our design reduces the diagnosis complexity from O(N) to O(1). For both testing and diagnosis, the hardware overhead for our approach is only about 0.43% for 16-bit numbers regardless of the FFT network size.

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        cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
        IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 10, Issue 3
        June 2002
        182 pages

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        IEEE Educational Activities Department

        United States

        Publication History

        Published: 01 June 2002

        Author Tags

        1. C-testable
        2. M-testable
        3. butterfly network
        4. design-for-diagnosability
        5. design-for-testability
        6. diagnosis
        7. fast Fourier transform (FFT)
        8. fault tolerance
        9. logic testing

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        • (2006)Diagnosis and Design for Diagnosability for Internet RoutersProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.51(761-768)Online publication date: 27-Mar-2006

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