This paper proposes AdaTest, a novel adaptive test pattern generation framework for efficient and reliable Hardware Trojan (HT) detection. HT is a backdoor attack that tampers with the design of victim integrated circuits (ICs). AdaTest improves the ...

Hardware Trojans have emerged as great threat to the trustability of modern electronic systems. A deployed electronic system with one or more undetected Hardware Trojan-infected components can cause grave harm, ranging from personal information loss to ...

Hardware Trojan attack in the form of malicious modification of a design has emerged as a major security threat. Side-channel analysis has been investigated as an alternative to conventional logic testing to detect the presence of hardware Trojans. ...

Reverse Engineering (RE) has been historically considered as a powerful approach to understand electronic hardware in order to gain competitive intelligence or accomplish piracy. In recent years, it has also been looked at as a way to authenticate ...

In component testing for a single function, a functional black box testing based on specification of the function and a white box testing based on the program structure are performed. However, It is difficult to verify a logical correctness of the ...

Mutation testing is widely recognized as being extremely powerful, but is considered difficult to automate enough for practical use. This paper theoretically addresses two possible reasons for this: the generation of redundant mutants and the lack of ...

When testing a Boolean expression, one should consider also the constraints among the variables contained in it. Constraints model interdependence among the conditions in the expressions. Only tests that satisfy the constraints. i.e. valid tests, are ...

Chemically assembled electronic nanotechnology (CAEN) is under intense investigation as a possible alternative or complement to CMOS-based computing. CAEN is a form of molecular electronics that uses directed self-assembly and self-alignment to ...

The lack of electronic design automation tools for system-on-chip (SOC) test integration increases SOC development time and cost, so SOC test integration tools are important in the success of promoting SOC. We have stressed practical SOC test ...

In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular designs for test method for sequential circuits. However, for circuits with many flip-flops, it requires a long test application time and high test-...

In this paper, we first propose a novel design-for-testability approach based on M-testability conditions for module-level systolic fast Fourier transform (FFT) arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a ...

We consider offline testing, design-for-testability, and diagnosis for fast Fourier transform (FFT) networks. A practical FFT chip can contain millions of gates, so effective testing and fault-tolerance techniques usualiy are required in order to ...

Abstract: Testing is a crucial part of the development of highly dependable systems. In this paper we consider testing of an implementation that is intended to satisfy a boolean formula. In the literature, specification-based testing has been suggested ...

Opens in interconnection paths disconnect the driven gate(s) from the driving gate. Detectability conditions to test full opens in interconnections are investigated. It has been found that the detectability of this defect depends strongly on the signals ...

We describe three parameters of output sequences of synchronous sequential circuits that can be used for fault diagnosis of such circuits. These parameters can replace the use of complete or partial output sequences for diagnosis. We investigate the ...

Asynchronous fine-grain pipeline circuits with dynamic gates are increasingly being used for high-performance datapath design in both synchronous and asynchronous processors. The dynamic gates intrinsically have storage elements for their outputs, which ...

A new multiple-valued current-mode (MVCM) integrated circuit based on dual-rail differential logic, whose current-driving capability is high at a low supply voltage, is proposed to realize a totally self-checking circuit and an asynchronous-control ...

Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor. However, domino logic suffers from several problems and one of the most notable ones is the charge ...

The proliferation of both partially depleted silicon-on-insulator (PDSOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between ...

A Built-In Self-Test (BIST) methodology and a test pattern generation (TPG) architecture for testing static random access memory (SRAM) interconnect at board level via IEEE 1149.1 Boundary Scan (BS) Architecture are presented. Due to the expense and ...