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Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links

Published: 01 February 2017 Publication History

Abstract

To maximize the utilization of the available networks-on-chip (NoCs) link bandwidth, partially faulty links with low fault level should be utilized while heavily defected (HD) links should be deactivated and dealt with by means of a fault tolerant routing algorithm. To reach this target, we make the following contributions in this paper: 1) we propose a flit serialization (FS) method to efficiently utilize partially faulty links. The FS approach divides the links into a number of equal width sections, and serializes sections of adjacent flits to transmit them on all fault-free link sections to mitigate the unbalance between the flit size and the actual link bandwidth; 2) we propose the link augmentation with one redundant section as a low cost mechanism to mitigate the FS drawback that a link’s available bandwidth is reduced even if it contains only one faulty wire; and 3) we deactivate HD links when their fault level exceed a certain threshold to diminish congestion caused by HD links. The optimal threshold is derived by comparing the zero load packet transmission latency on the HD links and that on the shortest alternative path. Our proposal is evaluated with synthetic traffic and PARSEC benchmarks. Experimental results indicate that the FS method can achieve lower area*power/saturation_throughput value than all state of the art link fault tolerant strategies. With a redundant section in each link, the NoC saturation throughput can be largely improved than just utilizing FS, e.g., 18% when 10% of the NoC wires are broken. Simulation results we obtained at various wire broken rate configurations indicate that we achieve the highest saturation throughput if 4- or 8-section links with a flit transmission latency longer than four cycles are deactivated.

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 36, Issue 2
February 2017
155 pages

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Published: 01 February 2017

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