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NoC Interconnect Yield Improvement Using Crosspoint Redundancy

Published: 04 October 2006 Publication History

Abstract

Systems-on-chip integrate increasingly larger numbers of pre-designed cores interconnected through complex communication fabrics. For nanometer-scale VLSI processes (45 nm and below), it is difficult to guarantee correct fabrication with an acceptable yield without employing design techniques that take into account the intrinsic existence of manufacturing defects. In order to improve the yield and reliability of multi-core SoCs, their interconnect infrastructures must be designed such that fabrication and life-time faults can be tolerated. In this work we present a self-repair method for the interconnect fabrics of integrated multi-core systems. Our method is based on the use of redundant links and crosspoints, and improves both post-manufacturing yield and life-time reliability of on-chip communication fabrics. Our method can provide a significant interconnect yield improvement (up to 72% in our experiments), and allows fine-tuning of yield versus redundant components.

Cited By

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  • (2017)Towards Maximum Utilization of Remained Bandwidth in Defected NoC LinksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.257068036:2(285-298)Online publication date: 1-Feb-2017
  • (2013)Methods for fault tolerance in networks-on-chipACM Computing Surveys (CSUR)10.1145/2522968.252297646:1(1-38)Online publication date: 11-Jul-2013
  • (2012)Addressing link degradation in noc-based ULSI designsProceedings of the 18th international conference on Parallel processing workshops10.1007/978-3-642-36949-0_36(327-336)Online publication date: 27-Aug-2012
  • Show More Cited By

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Information

Published In

cover image Guide Proceedings
DFT '06: Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
October 2006
573 pages
ISBN:076952706X

Publisher

IEEE Computer Society

United States

Publication History

Published: 04 October 2006

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Cited By

View all
  • (2017)Towards Maximum Utilization of Remained Bandwidth in Defected NoC LinksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.257068036:2(285-298)Online publication date: 1-Feb-2017
  • (2013)Methods for fault tolerance in networks-on-chipACM Computing Surveys (CSUR)10.1145/2522968.252297646:1(1-38)Online publication date: 11-Jul-2013
  • (2012)Addressing link degradation in noc-based ULSI designsProceedings of the 18th international conference on Parallel processing workshops10.1007/978-3-642-36949-0_36(327-336)Online publication date: 27-Aug-2012
  • (2010)A methodology for the characterization of process variation in NoC linksProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871092(685-690)Online publication date: 8-Mar-2010
  • (2010)Transient and Permanent Error Co-management Method for Reliable Networks-on-ChipProceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip10.1109/NOCS.2010.24(145-154)Online publication date: 3-May-2010
  • (2009)Adaptive router architecture based on traffic behavior observabilityProceedings of the 2nd International Workshop on Network on Chip Architectures10.1145/1645213.1645219(17-22)Online publication date: 12-Dec-2009

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