research-article

Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control

Author:

Augustus K. UhtAuthors Info & Claims

IEEE Transactions on Computers, Volume 54, Issue 2

Pages 132 - 140

https://doi.org/10.1109/TC.2005.34

Published: 01 February 2005 Publication History

Abstract

Uniprocessor designs have always assumed worst-case operating conditions to set the operating clock frequency and, hence, performance. However, much more performance can be obtained under typical operating conditions through experimentation, but such increased frequency operation is subject to the possibility of system failure and, hence, data loss/corruption. Further, mobile CPUs such as those in cell phones/internet browsers do not adapt to their current surroundings (varying temperature conditions, etc.) so as to increase or decrease operating frequency to maximize performance and/or allow operation under extreme conditions. We present a digital hardware design technique realizing adaptive clock-frequency performance-enhancing digital hardware; the technique can be tuned to approximate performance maximization. The cost is low and the design is straightforward. Experiments are presented evaluating such a design in a pipelined uniprocessor realized in a Field Programmable Gate Array (FPGA).

References

[1]

AMD, “AMD PowerNow!(TM) Technology Brief,” Advanced Micro Devices, Inc., 2003, http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Power_Now2.pdf.

[2]

F. Boyer M. Aboulhamid Y. Savaria and I. Bennour, “Optimal Design of Synchronous Circuits Using Software Pipelining Techniques,” Proc. 1998 Int'l Conf. Computer Design, 1998.

Digital Library

[3]

T.D. Burd T.A. Pering A.J. Stratakos and R.W. Brodersen, “A Dynamic Voltage Scaled Microprocessor System,” IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1571-1580, Nov. 2000.

[4]

D.M. Chapiro, “Globally-Asynchronous Locally-Synchronous Systems,” PhD thesis, Computer Science Dept., Stanford Univ., Oct. 1984.

Digital Library

[5]

M.J. Flynn P. Hung and K. Rudd, “Deep-Submicron Microprocessor Design Issues,” IEEE Micro, July-Aug. 1999.

Digital Library

[6]

S. Furber, “Asynchronous Logic,” IberChip, Feb. 1996.

[7]

R. Ginosar and R. Kol, “Adaptive Synchronization,” Proc. 1998 Int'l Conf. Computer Design, 1998.

[8]

Intel Staff, “Get a Notebook that Enables Extended Battery Life,” Intel Corp., 2003, http://www.intel.com/products/mobile technology/battery.htm.

[9]

Intel Staff, “Intel® Low-Power Technologies,” Intel Corp., 2003, http://www.intel.com/ebusiness/products/related_mobile/wp021601_sum.htm?iid=ipp_battery+press_lowpow.

[10]

A. Kondratyev and K. Lwin, “Design of Asynchronous Circuits Using Synchronous CAD Tools,” IEEE Design and Test of Computers, vol. 19, no. 4, pp. 107-117, July/Aug. 2002.

Digital Library

[11]

T. Kuroda K. Suzuki S. Mita T. Fujita F. Yamane F. Sano A. Chiba Y. Watanabe K. Matsuda T. Maeda T. Sakurai and T. Furuyama, “Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design,” IEEE J. Solid-State Circuits, vol. 33,no. 3, pp. 454-462, Mar. 1998.

[12]

C. Leiserson and J. Saxe, “Retiming Synchronous Circuitry,” Algorithmica, vol. 1, pp. 3-35, 1991.

[13]

A.J. Martin, “Design of an Asynchronous Microprocessor,” Technical Report CS-TR-89-02, Computer Science Dept., California Inst. Technology, Pasadena, 1989.

Digital Library

[14]

A. Merchant B. Melamed E. Schenfeld and B. Sengupta, “Analysis of a Control Mechanism for a Variable Speed Processor,” IEEE Trans. Computers, vol. 45, no. 7, pp. 968-976, July 1996.

Digital Library

[15]

M. Miyazaki J. Kao and A. Chandrakasan, “A 175mV Multiply-Accumulate Unit Using an Adaptive Supply Voltage and Body Bias (ASB) Architecture,” Proc. Int'l Solid-State Circuits Conf. (ISSCC), Feb. 2002.

[16]

S.F. Oberman H. Al-Twaijry and M.J. Flynn, “The SNAP Project: Design of Floating Point Arithmetic Units,” Proc. 13th IEEE Symp. Computer Arithmetic, July 1997.

Digital Library

[17]

M. Olivieri A. Trifiletti and A. De Gloria, “A Low-Power Microcontroller with On-Chip Self-Tuning Digital Clock Generator for Variable-Load Applications,” Proc. 1999 Int'l Conf. Computer Design, 1999.

Digital Library

[18]

D.A. Patterson and J.L. Hennessy, Computer Architecture: A Quantitative Approach, first ed. San Mateo, Calif.: Morgan Kaufman Publishers, 1990.

Digital Library

[19]

A.E. Sjogren and C.J. Myers, “Interfacing Synchronous and Asynchronous Modules within a High-Speed Pipeline,” Proc. 17th Conf. Advanced Research in VLSI (ARVLSI '97), pp. 47-61, 1997.

Digital Library

[20]

I.E. Sutherland, “Micropipelines,” Comm. ACM, vol. 32, no. 6, pp.nbsp720-738, June 1989.

Digital Library

[21]

H. Suzuki W. Jeong and K. Roy, “Low Power Adder with Adaptive Supply Voltage,” Proc. Int'l Conf. Computer Design (ICCD 2003), Oct. 2003.

Digital Library

[22]

N. Tzartzanis W. Walker H. Nguyen and A. Inoue, “A 34-Word 64b 10R/6W Write-Through Self-Timed Dual-Supply-Voltage Register File,” Proc. Int'l Solid-State Circuits Conf. (ISSCC), Feb. 2002.

[23]

A.K. Uht, “Achieving Typical Delays in Synchronous Systems via Timing Error Toleration,” Technical Report 032000-0100, Dept. of Electrical and Computer Eng., Univ. of Rhode Island, Kingston, Mar. 2000.

[24]

A.K. Uht, “ICED Canned CPU-IcpuED,” http://www.ele.uri. edu/iced/protosys/canned/cpu/iced-canned-cpu.html, June 2004.

[25]

A.K. Uht, “TEAtime Prototype Test Program Listing,” http://www.ele.uri.edu/~uht/research/TEAtime/BMK2.LST, June 2004.

[26]

A.K. Uht, “Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control,” Proc. SSGRR-2003w Int'l Conf. Advances in Infrastructure for e-Business, e-Education, e-Science, e-Medicine, and Mobile Technologies on the Internet, Jan. 2003.

[27]

A.K. Uht, “Going Beyond Worst-Case Specs with TEAtime,” Computer, vol. 37, no. 3, pp. 51-56, Mar. 2004.

Digital Library

Cited By

Villa OJohnson DO'Connor MBolotin ENellans DLuitjens JSakharnykh NWang PMicikevicius PScudiero AKeckler SDally WDamkroger TDongarra J(2014)Scaling the power wallProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1109/SC.2014.73(830-841)Online publication date: 16-Nov-2014
https://dl.acm.org/doi/10.1109/SC.2014.73
Sarrazin SEvain Sde Barros Naviner LBonhomme YGherman VMacii E(2013)Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detectionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485550(1077-1082)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485550
Park JChaudhari AAbraham JMacii E(2013)Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processorProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485351(254-257)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485351
Show More Cited By

Index Terms

Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
2. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Emerging technologies

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 54, Issue 2

February 2005

144 pages

ISSN:0018-9340

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Copyright © 2005.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 February 2005

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Cited By

Villa OJohnson DO'Connor MBolotin ENellans DLuitjens JSakharnykh NWang PMicikevicius PScudiero AKeckler SDally WDamkroger TDongarra J(2014)Scaling the power wallProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1109/SC.2014.73(830-841)Online publication date: 16-Nov-2014
https://dl.acm.org/doi/10.1109/SC.2014.73
Sarrazin SEvain Sde Barros Naviner LBonhomme YGherman VMacii E(2013)Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detectionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485550(1077-1082)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485550
Park JChaudhari AAbraham JMacii E(2013)Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processorProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485351(254-257)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485351
Park JAbraham JChang NNakamura HInoue KOsada KPoncino M(2011)A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systemsProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016894(391-396)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.5555/2016802.2016894
Banñeres DCortadella JKishinevsky MBenini LDe Micheli GAl-Hashimi BMueller W(2009)Variable-latency design by function speculationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875026(1704-1709)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1875026

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