research-article

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection

Authors:

Sébastien Sarrazin,

Lirida Alves de Barros Naviner,

Yannick Bonhomme,

Valentin GhermanAuthors Info & Claims

DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 1077 - 1082

Published: 18 March 2013 Publication History

Abstract

This paper presents new scan solutions with low latency overhead and on-line monitoring support. Shadow flip-flops with scan design are associated to system flip-flops in order to (a) provide concurrent delay fault detection and (b) avoid the scan chain insertion of system flip-flops. A mixed scan architecture is proposed which involves flip-flops with shadow scan design at the end of timing-critical paths and flip-flops with standard scan at non-critical locations. In order to preserve system controllability during test, system flip-flops with shadow scan can be set in scan mode and selectively reset before switching to capture mode. It is shown that shadow scan design with asynchronous set and reset may have a lower latency overhead than standard scan design. A shadow scan solution is proposed which, in addition to concurrent delay fault detection, provides simultaneous scan and capture capability.

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Cited By

Pomeranz I(2016)N-Detection Test Sets for Circuits with Multiple Independent Scan ChainsACM Transactions on Design Automation of Electronic Systems10.1145/289751421:4(1-15)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2897514
Pomeranz I(2016)Design-for-Testability for Functional Broadside Tests under Primary Input ConstraintsACM Transactions on Design Automation of Electronic Systems10.1145/283123121:2(1-18)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2831231

Index Terms

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware

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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe

March 2013

1944 pages

ISBN:9781450321532

General Chair:
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 18 March 2013

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DATE 13

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE 13: Design, Automation and Test in Europe

March 18 - 22, 2013

Grenoble, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Pomeranz I(2016)N-Detection Test Sets for Circuits with Multiple Independent Scan ChainsACM Transactions on Design Automation of Electronic Systems10.1145/289751421:4(1-15)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2897514
Pomeranz I(2016)Design-for-Testability for Functional Broadside Tests under Primary Input ConstraintsACM Transactions on Design Automation of Electronic Systems10.1145/283123121:2(1-18)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2831231

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