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CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors

Published: 13 November 2010 Publication History

Abstract

Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based on workload requirements. However, accurate allocation of power to these voltage/frequency islands based on time varying workload characteristics as well as controlling the power consumption at the provisioned power level is quite non-trivial. Toward this end, we propose a two-tier feedback-based control theoretic solution. Our first-tier consists of a global power manager that allocates power targets to individual islands based on the workload dynamics. The power consumptions of these islands are in turn controlled by a second-tier, consisting of local controllers that regulate island power using dynamic voltage and frequency scaling in response to workload requirements.

References

[1]
Intel pentium m processor on 90 nm process with 2-mb l2 cache datasheet, january 2006. http://download.intel.com/design/mobile/ datashts/30218908.pdf.
[2]
C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008.
[3]
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De. Parameter variations and impact on circuits and microarchitecture. In DAC '03: Proceedings of the 40th annual Design Automation Conference, 2003.
[4]
K. A. Bowman, A. R. Alameldeen, S. T. Srinivasan, and C. B. Wilkerson. Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. In Proceedings of the International Symposium on Low Power Electronics and Design, 2007.
[5]
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. SIGARCH Comput. Archit. News, 28(2), 2000.
[6]
A. Das, S. Ozdemir, G. Memik, and A. Choudhary. Evaluating voltage islands in cmps under process variations. In ICCD '07: Proceedings of the International Conference on Computer Design, 2007.
[7]
R. Das, J. O. Kephart, C. Lefurgy, G. Tesauro, D. W. Levine, and H. Chan. Autonomic multi-agent management of power and performance in data centers. In Proceedings of the International Conference on Autonomous agents and multiagent systems, 2008.
[8]
J. D. Davis, J. Laudon, and K. Olukotun. Maximizing cmp throughput with mediocre cores. In PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, 2005.
[9]
J. Donald and M. Martonosi. Techniques for multicore thermal management: Classification and new exploration. In ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture, 2006.
[10]
G. F. Franklin, M. L. Workman, and D. Powell. Digital Control of Dynamic Systems. Addison-Wesley Longman Publishing Co., Inc., 1997.
[11]
S. Garg and D. Marculescu. System-level throughput analysis for process variation aware multiple voltage-frequency island designs. ACM Trans. Des. Autom. Electron. Syst., 13(4), 2008.
[12]
M. Gomaa, M. D. Powell, and T. N. Vijaykumar. Heat-and-run: leveraging smt and cmp to manage power density through the operating system. SIGOPS Oper. Syst. Rev., 38(5), 2004.
[13]
J. L. Hellerstein, Y. Diao, S. Parekh, and D. M. Tilbury. Feedback Control of Computing Systems. John Wiley & Sons, 2004.
[14]
S. Herbert and D. Marculescu. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. In ISLPED '07: Proceedings of the International Symposium on Low power Electronics and Design, 2007.
[15]
S. Herbert and D. Marculescu. Variation-aware dynamic voltage/frequency scaling. In Proceedings of the International Symposium on High-Performance Computer Architecture, 2009.
[16]
E. Humenay, D. Tarjan, and K. Skadron. Impact of process variations on multicore performance symmetry. In Proceedings of the conference on Design, Automation and Test in Europe, 2007.
[17]
C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget. In Proceedings of the International Symposium on Microarchitecture, 2006.
[18]
A. Iyer and D. Marculescu. Power and performance evaluation of globally asynchronous locally synchronous processors. In ISCA '02: Proceedings of the 29th annual international symposium on Computer architecture, 2002.
[19]
A. Iyer and D. Marculescu. Power efficiency of voltage scaling in multiple clock, multiple voltage cores. In Proceedings of the International Conference on Computer-Aided Design, 2002.
[20]
P. Juang, Q. Wu, L.-S. Peh, M. Martonosi, and D. W. Clark. Coordinated, distributed, formal energy management of chip multiprocessors. In ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design, 2005.
[21]
W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), 2008.
[22]
D. E. Lackey et al. Managing power and performance for system-on-chip designs using voltage islands. In ICCAD '02: Proceedings of the 2002 IEEE/ACM Intn. Conf. on Comp.-aided design, 2002.
[23]
J. Li and J. F. Martinez. Dynamic power-performance adaptation of parallel computation on chip multiprocessors. In HPCA '06: Proceedings of the Twelfth International Symposium on High-Performance Computer Architecture, 2006.
[24]
G. Magklis, P. Chaparro, J. González, and A. González. Independent front-end and back-end dynamic voltage scaling for a gals microarchitecture. In ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design, 2006.
[25]
P. S. Magnusson et al. Simics: A full system simulation platform. Computer, 35(2):50-58, 2002.
[26]
M. Martin et al. Multifacet's general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput. Archit. News, 2005.
[27]
C. McNairy and D. Soltis. Itanium 2 processor microarchitecture. IEEE Micro, 23(2), 2003.
[28]
K. Meng, R. Joseph, R. P. Dick, and L. Shang. Multioptimization power management for chip multiprocessors. In PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques, 2008.
[29]
M. Monchiero, R. Canal, and A. Gonzalez. Power/performance/thermal design-space exploration for multicore architectures. IEEE Trans. Parallel Distrib. Syst., 19(5), 2008.
[30]
K. Niyogi and D. Marculescu. Speed and voltage selection for gals systems based on voltage/frequency islands. In ASP-DAC '05: Proceedings of the 2005 conference on Asia South Pacific design automation, 2005.
[31]
R. Raghavendra, P. Ranganathan, V. Talwar, Z. Wang, and X. Zhu. No"power" struggles: coordinated multi-level power management for the data center. SIGARCH Comput. Archit. News, 36(1), 2008.
[32]
L. Ramos and R. Bianchini. C-oracle: Predictive thermal management for data centers. In HPCA '08: Proceedings of the 14th IEEE Intern. Symp. on High-Performance Computer Archit., 2008.
[33]
G. Semeraro et al. Dynamic frequency and voltage control for a multiple clock domain microarchitecture. In MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, 2002.
[34]
G. Semeraro et al. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In HPCA '02: Proceedings of the 8th International Symposium on High-Performance Computer Architecture, 2002.
[35]
K. Skadron, M. R. Stan, K. Sankaranarayanan, W. H. S. Velusamy, and D. Tarjan. Temperature-aware microarchitecture: Modeling and implementation. ACM Trans. Archit. Code Optim. (TACO), 2004.
[36]
R. Teodorescu and J. Torrellas. Variation-aware application scheduling and power management for chip multiprocessors. In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, 2008.
[37]
X. Wang and M. Chen. Cluster-level feedback power control for performance optimization. In HPCA '08: Proceedings of the 14th IEEE International Symposium on High-Performance Computer Architecture, 2008.
[38]
Y. Wang, K. Ma, and X. Wang. Temperature-constrained power control for chip multiprocessors with online model estimation. In ISCA '09: Proceedings of the 36th International Symposium on Computer Architecture, 2009.
[39]
Q. Wu, P. Juang, M. Martonosi, and D. W. Clark. Formal online methods for voltage/frequency control in multiple clock domain microprocessors. SIGARCH Comput. Archit. News, 32(5):248-259, 2004.
[40]
Z. Yu and B. Baas. Implementing tile-based chip multiprocessors with gals clocking styles. ICCD '06: International Conference on Computer Design, 2006.
[41]
Z. Yu and B. M. Baas. Performance and power analysis of globally asynchronous locally synchronous multi-processor systems. In ISVLSI '06: Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2006.
[42]
Y. Zhang et al. Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects, Tech. Report CS-2003-05, Univ. of Virginia, 2003.

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  1. CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors

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    cover image ACM Conferences
    SC '10: Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
    November 2010
    634 pages
    ISBN:9781424475599

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    Published: 13 November 2010

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    SC '10 Paper Acceptance Rate 51 of 253 submissions, 20%;
    Overall Acceptance Rate 1,516 of 6,373 submissions, 24%

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    • (2022)TokenSmart: Distributed, Scalable Power Management in the Many-core EraACM Transactions on Architecture and Code Optimization10.1145/355976220:1(1-26)Online publication date: 17-Nov-2022
    • (2021)FlexProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00033(319-332)Online publication date: 14-Jun-2021
    • (2019)Closed-Loop System to Guarantee Battery Lifetime for Mobile Video ApplicationsIEEE Transactions on Consumer Electronics10.1109/TCE.2019.289117865:1(18-27)Online publication date: 1-Feb-2019
    • (2018)SPECTRACM SIGPLAN Notices10.1145/3296957.317319953:2(169-183)Online publication date: 19-Mar-2018
    • (2018)SPECTRProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173199(169-183)Online publication date: 19-Mar-2018
    • (2017)Fast Power and Energy Management for Future Many-Core SystemsACM Transactions on Modeling and Performance Evaluation of Computing Systems10.1145/30865042:3(1-31)Online publication date: 5-Sep-2017
    • (2016)Using multiple input, multiple output formal control to maximize resource efficiency in architecturesACM SIGARCH Computer Architecture News10.1145/3007787.300120744:3(658-670)Online publication date: 18-Jun-2016
    • (2016)Scalable Power Management for On-Chip Systems with Malleable ApplicationsIEEE Transactions on Computers10.1109/TC.2016.254063165:11(3398-3412)Online publication date: 1-Nov-2016
    • (2016)Using multiple input, multiple output formal control to maximize resource efficiency in architecturesProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.63(658-670)Online publication date: 18-Jun-2016
    • (2015)Scalable Global Power Management Policy Based on Combinatorial Optimization for MultiprocessorsACM Transactions on Embedded Computing Systems10.1145/281140414:4(1-24)Online publication date: 8-Dec-2015
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