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Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems

Published: 02 March 2006 Publication History

Abstract

This paper investigates the performance and power dissipation of Globally Asynchronous Locally Synchronous (GALS) multi-processor systems. We show that communication loops are a source of significant throughput degradation in communications links and that there is no degradation whatsoever under certain conditions for one-way links, and that it is possible to design GALS multi-processors without this performance penalty. Independent clock domains and unbalanced computation in the GALS multiprocessor allow scaling of the clock frequency and supply voltage to achieve high energy efficiency. The synchronization overhead between independent clock domains results in a less than 1% performance reduction compared to a globally synchronous system over a number of DSP and numerical applications. Clock and voltage scaling can achieve an approximately 40% power savings with no reduction of performance. These results compare favorably with the 25% power savings and more than 10% performance reduction reported for GALS uniprocessors.

Cited By

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  • (2010)A low-area multi-link interconnect architecture for GALS chip multiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201791218:5(750-762)Online publication date: 1-May-2010
  • (2010)CPM in CMPsProceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis10.1109/SC.2010.15(1-12)Online publication date: 13-Nov-2010
  • (2009)High performance, energy efficiency, and scalability with GALS chip multiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200194717:1(66-79)Online publication date: 1-Jan-2009
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        cover image Guide Proceedings
        ISVLSI '06: Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
        March 2006
        ISBN:0769525334

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        IEEE Computer Society

        United States

        Publication History

        Published: 02 March 2006

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        • (2010)A low-area multi-link interconnect architecture for GALS chip multiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201791218:5(750-762)Online publication date: 1-May-2010
        • (2010)CPM in CMPsProceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis10.1109/SC.2010.15(1-12)Online publication date: 13-Nov-2010
        • (2009)High performance, energy efficiency, and scalability with GALS chip multiprocessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200194717:1(66-79)Online publication date: 1-Jan-2009
        • (2007)AsAPIEEE Micro10.1109/MM.2007.2927:2(34-45)Online publication date: 1-Mar-2007

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