article

Hierarchical circuit-switched NoC for multicore video processing

Authors:

Shu-Hsuan Chou,

Chien-Chih Chen,

Tay-Jyi LinAuthors Info & Claims

Microprocessors & Microsystems, Volume 35, Issue 2

Pages 182 - 199

https://doi.org/10.1016/j.micpro.2010.09.009

Published: 01 March 2011 Publication History

Abstract

Today's prevailing video systems demand extreme performance that can be efficiently supported by parallel computing engines. This paper presents a novel hierarchical circuit-switched ring network on chip (called HrNoC) for the parallel engines, of which the cost, power, and latency have been extensively optimized from bottom up. First, a communication scheme ''wave'' is proposed for both intra-ring and inter-ring routing-paths built with rapid stream transactions. Then, a cost-effective bridge featuring deterministic packet traversal and deadlock avoidance is designed for flexible inter-ring connections. Finally, varied configurations of hierarchical rings are exploited by system specification and application mapping. In experiments, the proposed HrNoC on a 16-core multicore system performs about 50% latency reduction, 1/3 area cost, and 1/5 power consumption, compared with a packet-switched mesh NoC.

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Cited By

Yahya MWu NAli ZKhizar Y(2019)Optical Versus Electrical: Performance Evaluation of Network On-Chip Topologies for UWASN Manycore ProcessorsWireless Personal Communications: An International Journal10.1007/s11277-019-06630-5116:2(963-991)Online publication date: 1-Aug-2019
https://dl.acm.org/doi/10.1007/s11277-019-06630-5
Matos DReinbrecht CKreutz MPalermo GCarro LSusin A(2013)Hierarchical and multiple switching NoC with floorplan based adaptabilityProceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications10.1007/978-3-642-36812-7_17(179-184)Online publication date: 25-Mar-2013
https://dl.acm.org/doi/10.1007/978-3-642-36812-7_17

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Published In

cover image Microprocessors & Microsystems

Microprocessors & Microsystems Volume 35, Issue 2

March, 2011

215 pages

ISSN:0141-9331

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Copyright © Elsevier B.V. © 2010.

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Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 March 2011

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Cited By

Yahya MWu NAli ZKhizar Y(2019)Optical Versus Electrical: Performance Evaluation of Network On-Chip Topologies for UWASN Manycore ProcessorsWireless Personal Communications: An International Journal10.1007/s11277-019-06630-5116:2(963-991)Online publication date: 1-Aug-2019
https://dl.acm.org/doi/10.1007/s11277-019-06630-5
Matos DReinbrecht CKreutz MPalermo GCarro LSusin A(2013)Hierarchical and multiple switching NoC with floorplan based adaptabilityProceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications10.1007/978-3-642-36812-7_17(179-184)Online publication date: 25-Mar-2013
https://dl.acm.org/doi/10.1007/978-3-642-36812-7_17

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