The 2D mesh topology-based Network-on-Chip (NoC) is a prevalent structure in System-on-Chip (SoC) designs, offering implementation and fabrication benefits. However, increased NoC scale leads to longer communication paths, more hops, and higher ...

In modern chip designs with multiple processors, network-on-chip (NoC) has emerged as a critical solution, offering scalability, flexibility, modularity, and efficiency. However, a significant challenge in application mapping is ...

Application mapping is one of the early stage design processes aimed to improve the performance of Network-on-Chip. Mapping is an NP-hard problem. A massive amount of high-quality supervised data is required to solve the application mapping problem using ...

Advancement in very large scale integration (VLSI) technologies and the ever-shrinking size of the transistors have led the semiconductor designers to create a multiprocessor system on chips. Network on chip (NoC) provides an efficient ...

Technology advancement in semiconductors enables integration of large number of cores on a single chip that leads to the design and development of Multi-Processor System on Chip (MPSoC). In Network-on-Chip (NoC) based MPSoCs dozens and even 100s ...

Communication cost in terms of energy consumption and network latency, along with the dynamic allocation time of the tasks and their execution time, is the primary design concern of a run-time mapping and scheduling strategy that may significantly ...

Some previous researches have explored the application mappings for network-on-chip to reduce the power consumption and the network latency. However, some of these previous application mapping algorithms only find the local optimal result instead ...

Network on chip (NoC) has been of great interest in recent years. However, according to the recent studies, high communication cost has been raised as the one most important challenges in mapping process in NoC. In order to address these issues, ...

Advances in digital system manufacturing and increasing demand for high-speed applications have urged designers on using multiprocessor systems. Network on chip (NOC) is an important architecture used for implementing multiprocessor systems. The ...

Optical on-chip network provides a high-performance on-chip communication platform, while several reliability challenges, such as insertion loss and crosstalk noise may limit their scalability. In this paper, we propose an insertion ...

Dynamic reconfiguration provides flexibility in the design and management of reconfigurable computing (RC) systems such that numerous applications would be mapped into limited resources simultaneously. As the mapping is a computationally intensive ...

Application mapping in multicore embedded systems plays a central role in their energy-efficiency. The present paper deals with this issue by focusing on the prediction of performance and energy consumption, induced by task and data ...

Application mapping is a critical phase in NoC design because of the running time, the network latency and the power consumption. In order to reduce these problems of applications running on multicore architecture, we propose a novel application ...

Design at the Electronic System-Level tackles the increasing complexity of embedded systems by raising the level of abstraction in system specification and modeling. Two important steps in this process are evaluation of a single design ...

In this paper, we propose an optimized, search based near-optimal mapping heuristic, named as ONMAP for mapping real time embedded application workloads on 2D based on-chip interconnection network platforms. ONMAP exploits NMAP, a well-known and fast ...

In this paper, the influence of the mapping algorithm on the physical layer parameters and photonic network-on-chip performance is demonstrated. Four mapping algorithms, namely hop count, congestion, no-turn, and turn, have been suggested. The proposed ...

In Network-on-Chip based multi-core systems, application mapping is a critical issue as it affects the overall system performance in terms of average packet delay (APD) and system reliability. As the number of Intellectual Property (IP)...

• Proposed a reliability model taking into consideration the temperature of both cores and routers.

This paper addresses the problem of mapping tasks onto an FPGA-based many-core platform where the cores typically have a limited amount of memory and thus should be frequently overlaid with a small program block that implements a task. In this regard, ...

Many-core systems connected by 3D Network-on-Chips (NoC) are emerging as a promising computation engine for systems like cloud computing servers, big data systems, etc. Mapping applications at runtime to 3D NoCs is the key to maintain high throughput of ...

The Finite Element Method (FEM) is a common numerical technique used for solving Partial Differential Equations on large and unstructured domain geometries. Numerical methods for FEM typically use algorithms and data structures which exhibit an ...