article

Optimal transistor sizing for maximum yield in variation-aware standard cell design

Authors:

Mauro OlivieriAuthors Info & Claims

International Journal of Circuit Theory and Applications, Volume 44, Issue 7

Pages 1400 - 1424

https://doi.org/10.1002/cta.2167

Published: 01 July 2016 Publication History

Abstract

Process variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome yield of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst-case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits PDKs. The approach is demonstrated for a 40nm low-power standard threshold voltage Complementary Metal Oxide Semiconductor CMOS technology, for an intended operating temperature range [-40ï źC, 125ï źC] and supply voltage range [0.95V, 1.05V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis SPICE-level Monte Carlo analysis confirmed the estimated yield of the obtained circuits. Copyright © 2015 John Wiley & Sons, Ltd.

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Cited By

Compassi-Severo LDe-Oliveira Tde Aguirre PVan Noije WGirardi A(2024)Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass FiltersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333587732:2(205-218)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2023.3335877
Soares TNizer Rahmeier JDe Lima VLascasas LCosta Melo LVilela Neto O(2018)NMLSimJournal of Computational Electronics10.1007/s10825-018-1215-817:3(1370-1381)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1007/s10825-018-1215-8
Abbas ZOlivieri MRipp A(2016)Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradationsJournal of Computational Electronics10.1007/s10825-016-0878-215:4(1424-1439)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10825-016-0878-2

Optimal transistor sizing for maximum yield in variation-aware standard cell design
1. Hardware

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Published In

cover image International Journal of Circuit Theory and Applications

International Journal of Circuit Theory and Applications Volume 44, Issue 7

July 2016

131 pages

ISSN:0098-9886

EISSN:1097-007X

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John Wiley and Sons Ltd.

United Kingdom

Publication History

Published: 01 July 2016

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Cited By

Compassi-Severo LDe-Oliveira Tde Aguirre PVan Noije WGirardi A(2024)Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass FiltersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333587732:2(205-218)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TVLSI.2023.3335877
Soares TNizer Rahmeier JDe Lima VLascasas LCosta Melo LVilela Neto O(2018)NMLSimJournal of Computational Electronics10.1007/s10825-018-1215-817:3(1370-1381)Online publication date: 1-Sep-2018
https://dl.acm.org/doi/10.1007/s10825-018-1215-8
Abbas ZOlivieri MRipp A(2016)Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradationsJournal of Computational Electronics10.1007/s10825-016-0878-215:4(1424-1439)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10825-016-0878-2

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